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VLDB 2026 Research / reviewers in the wild / expert

William C. Brantley

dblp:20/1189 · DBLP profile ↗
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5ranked-venue papers
1as first author
1since 2021 · last 2023
0009-0002-6885-120XORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 1 first-author · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
High-performance computing · 43% Memory systems · 22% Processor architecture and microarchitecture · 11%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
High-performance computing › supercomputing
exascale computing		 0.922023
A Research Retrospective on AMD's Exascale Computing Journey · ISCA 2023
Design and Analysis of an APU for Exascale Computing · HPCA 2017
Memory systems
3d-stacked memory		 0.312017
Design and Analysis of an APU for Exascale Computing · HPCA 2017
GPUs and heterogeneous computing › heterogeneous architecture
accelerated processing unit		 0.312017
Design and Analysis of an APU for Exascale Computing · HPCA 2017
Hardware accelerators and domain-specific architectures › accelerator integration
CPU-GPU integration		 0.312017
Design and Analysis of an APU for Exascale Computing · HPCA 2017
Processor architecture and microarchitecture › multicore design
heterogeneous processor architecture		 0.312017
Design and Analysis of an APU for Exascale Computing · HPCA 2017
Memory systems › DRAM › DRAM architecture
high bandwidth memory		 0.312017
Design and Analysis of an APU for Exascale Computing · HPCA 2017
High-performance computing
supercomputing		 0.212023
A Research Retrospective on AMD's Exascale Computing Journey · ISCA 2023
Integrated circuit design › heterogeneous integration
chiplet-based design		 0.112017
Design and Analysis of an APU for Exascale Computing · HPCA 2017

Methods — techniques the papers use, named apart from their topics

architectural simulation · 0.3
YearPublicationVenuePosition
2023 A Research Retrospective on AMD's Exascale Computing Journey
abstract
The pace of advancement of the top-end supercomputers historically followed an exponential curve similar to (and driven in part by) Moore's Law. Shortly after hitting the petaflop mark, the community started looking ahead to the next milestone: Exascale. However, many obstacles were already looming on the horizon, such as the slowing of Moore's Law, and others like the end of Dennard Scaling had already arrived. Anticipating significant challenges for the overall high-performance computing (HPC) community to achieve the next 1000x improvement, the U.S. Department of Energy (DOE) launched the Exascale Computing Program to enable and accelerate fundamental research across the many technologies needed to achieve exascale computing.
Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Vignesh Adhinarayanan, Shaizeen Aga, Derrick Aguren, Varun Agrawal, Ashwin M. Aji, Johnathan Alsop, Paul T. Bauman, Bradford M. Beckmann, Majed Valad Beigi, Sergey Blagodurov, Travis Boraten, Michael Boyer, William C. Brantley, Noel Chalmers, Shaoming Chen, Michael L. Chu, David Cownie, Nicholas Curtis, Joris Del Pino, Nam Duong, Alexandru Dutu, Yasuko Eckert, Christopher Erb, Chip Freitag, Joseph L. Greathouse, Sudhanva Gurumurthi, Anthony Gutierrez, Khaled Hamidouche, Sachin Hossamani, Wei Huang 0004, Mahzabeen Islam, Nuwan Jayasena, John Kalamatianos, Onur Kayiran, Jagadish Kotra, Alan Lee, Daniel Lowell, Niti Madan, Abhinandan Majumdar, Nicholas Malaya, Srilatha Manne, Susumu Mashimo, Damon McDougall, Elliot Mednick, Michael Mishkin, Mark Nutter, Indrani Paul, Matthew Poremba, Brandon Potter, Kishore Punniyamurthy, Sooraj Puthoor, Steven E. Raasch, Karthik Rao, Gregory Rodgers, Marko Scrbak, Mohammad Seyedzadeh, John Slice, Vilas Sridharan, René van Oostrum, Eric Van Tassell, Abhinav Vishnu, Samuel Wasmundt, Mark Wilkening, Noah Wolfe, Mark Wyse, Adithya Yalavarti, Dmitri Yudanov
 ISCA16
2017 Design and Analysis of an APU for Exascale Computing
abstract
The challenges to push computing to exaflop levels are difficult given desired targets for memory capacity, memory bandwidth, power efficiency, reliability, and cost. This paper presents a vision for an architecture that can be used to construct exascale systems. We describe a conceptual Exascale Node Architecture (ENA), which is the computational building block for an exascale supercomputer. The ENA consists of an Exascale Heterogeneous Processor (EHP) coupled with an advanced memory system. The EHP provides a high-performance accelerated processing unit (CPU+GPU), in-package high-bandwidth 3D memory, and aggressive use of die-stacking and chiplet technologies to meet the requirements for exascale computing in a balanced manner. We present initial experimental analysis to demonstrate the promise of our approach, and we discuss remaining open research challenges for the community.
Thiruvengadam Vijayaraghavan, Yasuko Eckert, Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Bradford M. Beckmann, William C. Brantley, Joseph L. Greathouse, Wei Huang 0004, Arun Karunanithi, Onur Kayiran, Mitesh R. Meswani, Indrani Paul, Matthew Poremba, Steven E. Raasch, Steven K. Reinhardt, Greg Sadowski, Vilas Sridharan
 HPCA7
2010 SPEC MPI2007 - an application benchmark suite for parallel systems using MPI
abstract
Abstract The SPEC High‐Performance Group has developed the benchmark suite SPEC MPI2007 and its run rules over the last few years. The purpose of the SPEC MPI2007 benchmark and its run rules is to further the cause of fair and objective benchmarking of high‐performance computing systems. The rules help to ensure that the published results are meaningful, comparable to other results, and reproducible. MPI2007 includes 13 technical computing applications from the fields of computational fluid dynamics, molecular dynamics, electromagnetism, geophysics, ray tracing, and hydrodynamics. We describe the benchmark suite, and compare it with other benchmark suites. Copyright © 2009 John Wiley & Sons, Ltd.
Matthias S. Müller, Matthijs van Waveren, Ron Lieberman, Brian Whitney, Hideki Saito 0001, Kalyan Kumaran, John Baron, William C. Brantley, Chris Parrott, Tom Elken, Huiyu Feng, Carl Ponder
 Concurr. Comput. Pract. Exp.8
1985 RP3 Processor-Memory Element
William C. Brantley, Kevin P. McAuliffe, Jodi Weiss
 ICPP1
1985 The IBM Research Parallel Processor Prototype (RP3): Introduction and Architecture
Gregory F. Pfister, William C. Brantley, David A. George, Steve L. Harvey, Wally J. Kleinfelder, Kevin P. McAuliffe, Evelin S. Melton, V. Alan Norton, Jodi Weiss
 ICPP2