Multiple-Path Interference (MPI) is a major drawback of Time-of-Flight (ToF) sensors. Current methods resolving more than a single light bounce per pixel rely on the sequential acquisition of large amounts of data and are computationally expensive. These factors have precluded the development of a real-time multiple-path ToF camera to date. In this work we consider two hardware alternatives able to acquire all necessary raw data in a single shot. We introduce a unified signal processing pipeline that takes the single-shot raw data from any of these sensors as input and delivers an independent depth image per interfering path. We use the measurements to estimate the lowest-frequency Fourier coefficients of the scene response function, which can be ideally modeled as a train of Dirac delta functions. A robust parametric spectral estimation method allows us recovering the unknown parameters (distance and reflectivity of the targets) for all pixels in real time.

The photometric stereo method enables estimation of surface normals from images that have been captured using different but known lighting directions. The classical photometric stereo method requires at least three images to determine the normals in a given scene. However, this method cannot be applied to dynamic scenes because it is assumed that the scene remains static while the required images are captured. In this work, we present a dynamic photometric stereo method for estimation of the surface normals in a dynamic scene. We use a multi-tap complementary metal-oxide-semiconductor (CMOS) image sensor to capture the input images required for the proposed photometric stereo method. This image sensor can divide the electrons from the photodiode from a single pixel into the different taps of the exposures and can thus capture multiple images under different lighting conditions with almost identical timing. We implemented a camera lighting system and created a software application to enable estimation of the normal map in real time. We also evaluated the accuracy of the estimated surface normals and demonstrated that our proposed method can estimate the surface normals of dynamic scenes.

Recently, several varieties of image recognition systems using Fourier transform have been proposed. The salient benefit of using a Fourier transform is its position-independent image recognition capability. However, the operation of Fourier transform of high-resolution images is an extremely heavy operation. This paper therefore presents a proposal of image recognition systems using an optical Fourier transform on a dynamically reconfigurable vision architecture. This proposed system can recognize numerous images within an extremely short period using dynamic reconfiguration.

Recently, for use in autonomous vehicles and robots, demand has been increasing for high-speed image recognition that is superior to that of the human eye. However, to recognize numerous images quickly, such systems require many template images to be read out dynamically from memory. They must then be sent to a processor quickly. Achieving such high-speed real-time image recognition operation is difficult because of the bottleneck of the transfer between the memory and the processor. To alleviate that bottleneck, a dynamically reconfigurable vision architecture was proposed. This paper presents 16-gray scale image recognition operation of the proposed architecture.

This paper describes a low-power low-distortion pipeline ADC with 1.0V supply voltage. A cascade amp-sharing architecture and capacitor coupling class-AB amplifier are proposed for low-power dissipation under high-speed sampling. The capacitance coupling S/H stage suppresses the distortion caused by the insufficient gate-source voltage of sampling switches due to a low supply voltage. According to H-SPICE simulation results, the 10b 125MSample/s ADC in 90nm digital CMOS process achieves SNDR of 56dB with a power dissipation of only 21mW.

This paper presents the design and implementation of a one-chip camera device for capsule endoscopes. A prototype image sensor chip which has 320 times 240 effective pixels was fabricated using 0.25 mum CMOS image sensor process. This experimental chip integrates functional circuits required for capsule endoscopes and digital image transmission function. The integrated functional blocks include an image array, a timing generator, a clock generator, a voltage regulator, a 10b cyclic A/D converter, and a BPSK modulator. It can be operated autonomously with 3 pins (VDD, GND, and DATAOUT). With a 2.0 V power supply, the analog part consumes 950muW and the total power consumption at 2 frames per second (fps) is 2.6mW. Error-free image transmission over a distance of 48cm at 2.5Mbps corresponding to 2fps has been succeeded with inductive coupling

Circuit and device technologies for CMOS-based functional image sensors are reviewed and discussed. A key device technology that enhances the image quality of CMOS image sensors to be comparable to or even better than the CCD is a pinned photo diode. However, the performance of the CMOS image sensors also largely owes to the design of readout circuits. Several examples that successfully achieve the extreme performance using circuit techniques are reviewed in the aspects of sensitivity, noise, dynamic range and speed. For special functions such as 3-dimensional imaging, the development of new device technologies is also particularly important. As an example, a time-of-flight range finding CMOS imager with a modified CMOS process and a special pixel structure is presented

In this paper, motion vector (MV) estimation methods with high-speed intermediate pictures for low-power video compression are proposed. The intermediate pictures are obtained by a special type of CMOS image sensor. An adaptive iterative-search block matching is proposed to obtain precise MVs of video-rate pictures from high-speed intermediate pictures with the reduced computational complexity. The sensor captures high-speed intermediate pictures without destructing signal charge and video-rate pictures with full signal accumulation time. The proposed active pixel sensor using bidirectional multiple charge transfer is useful for the nondestructive intermediate imaging with a reduced fixed pattern noise. The image sensor chip has been implemented by using 0.35-/spl mu/m CMOS technology. It operates with 3.3 V and captures 480 frames/s high-speed nondestructive intermediate pictures and 30 frame/s fully accumulated video-rate pictures. The proposed adaptive iterative-search block matching has a comparable precision to a full search block matching with reduction of computational complexity by a factor of about 1/13, on average. It also reduces the data-loading rate from the memory by a factor of about 1/4.

This paper describes CMOS image sensors integrating video compression circuits. The on-sensor compression is particularly useful for the low-power design of moving picture compression hardware, which is demanded especially in the mobile computing and telephony. Recent progress of the CMOS image sensor technology allows us to realise the integration of high-performance image sensor and computational functions on a chip. An example of the CMOS image sensor with compression is described. Prospects of the CMOS image sensors with moving picture compression are discussed.

A CMOS smart image sensor LSI with video compression is presented. The proposed on-sensor compression scheme using an analog 2-D DCT processor is particularly useful to achieve low-power one-chip digital camera. A prototype image sensor LSI has been developed using 0.35 /spl mu/m double polysilicon, triple metal CMOS technology. Image coding using the implemented LSI has been demonstrated.

Presents a very-large-scale-integration (VLSI)-oriented high-speed multiplier design method based on carry-propagation-free addition trees and a circuit technique, so-called multiple-valued current-mode (MVCM) circuits. The carry-propagation-free addition method uses a redundant digit set such as /spl lcub/0,1,2,3/spl rcub/ and /spl lcub/0,1,2,3,4/spl rcub/. The number representations using such redundant digit sets are called redundant positive-digit number representations. The carry-propagation-free addition is written by three steps, and the adder can be designed directly and efficiently from the algorithm using MVCM circuits. The designed multiplier internally using the MVCM parallel adder with the digit set /spl lcub/0,1,2,3/spl rcub/ in radix 2 has attractive features on speed, regularity of the structure, and reduced complexities of active elements and interconnections. A prototype CMOS integrated circuit of the MVCM parallel adder has been implemented, and its stable operation has been confirmed. Other possible schemes of multipliers with redundant digit sets using MVCM technology are discussed.>