Inter-cell interference coordination (ICIC) has been widely studied for mitigating the effects of severe inter-cell interference (ICI) in cell- edge users. However, based on the scarcity of frequency resources in orthogonal multiple access systems, the ICIC methods proposed in the previous papers have difficulty in maintaining the overall performance and fairness of a system. Non-orthogonal multiple access (NOMA) is a promising radio access technology that can serve multiple users simultaneously with the same frequency resources. However, most previous work has not considered the ICI problem in NOMA systems. We propose a centralized adaptive ICIC framework for downlink NOMA systems, including a distributed clustering algorithm, a distributed power allocation algorithm, and a centralized frequency allocation algorithm. Simulation results demonstrate that the proposed framework outperforms all benchmark frameworks and can improve both the overall performance of a system and fairness among users.

In cellular networks, inter-cell interference is the main factor in the reduction of service quality for users, so intercell interference coordination (ICIC) has been widely studied to mitigate severe interference. However, in some previous work, cell- edge users are sacrificed to improve the performance of the overall system. Apart from this, most previous methods change the ICIC configuration frequently to achieve the optimal results, but in practice, the frequent ICIC reconfiguration results in large overhead for small cells. Thus, a centralized dynamic ICIC scheme is proposed in this work, including Q-learning assisted deep neural network based ICIC framework and Type-Balanced User Grouping algorithm. The simulation results show that the proposed ICIC scheme outperforms the benchmarks in both sparse and dense user distribution.

Power consumption is an important design issue of current embedded systems. It has been shown that the instruction cache accounts for a significant portion of the power dissipation of the whole chip. Several studies propose to add a cache (L0 cache) that is very small relative to the conventional L1 cache on chip for power optimization since a smaller cache has lower load capacitance. However, energy savings often come at the cost of performance degradation. In this paper, we propose a novel instruction cache architecture, the HotSpot cache, that achieves energy savings without sacrificing performance. The HotSpot cache identifies frequently accessed instructions dynamically and stores them in the L0 cache. Other instructions are placed only in the L1 cache. A steering mechanism is employed to direct an instruction to its allocated cache in the instruction fetch stage. The simulation results show that the HotSpot cache can achieve 52% instruction cache energy reduction on the average for a set of multimedia applications without performance degradation.

Prefetching is often used to overlap memory latency with computation for array-based applications. However, prefetching for pointer-intensive applications remains a challenge because of the irregular memory access pattern and pointer-chasing problem. In this paper, we proposed a cooperative hardware/software prefetching framework, the push architecture, which is designed specifically for linked data structures. The push architecture exploits program structure for future address generation instead of relying on past address history. It identifies the load instructions that traverse a LDS and uses a prefetch engine to execute them ahead of the CPU execution. This allows the prefetch engine to successfully generate future addresses. To overcome the serial nature of LDS address generation, the push architecture employs a novel data movement model. It attaches the prefetch engine to each level of the memory hierarchy and pushes , rather than pulls , data to the CPU. This push model decouples the pointer dereference from the transfer of the current node up to the processor. Thus a series of pointer dereferences becomes a pipelined process rather than a serial process. Simulation results show that the push architecture can reduce up to 100% of memory stall time on a suite of pointer-intensive applications, reducing overall execution time by an average 15%.