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Chia-Hsiaing Sung

dblp:20/2226 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 1976
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 81% Integrated circuit design · 19%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › VLSI testing
cellular array testing		 0.021976
Testable Sequential Cellular Arrays · IEEE Trans. Computers 1976
Tessellation Aspect of Combinational Cellular Array Testing · IEEE Trans. Computers 1974
Electronic design automation
hardware verification and test		 0.021976
Testable Sequential Cellular Arrays · IEEE Trans. Computers 1976
Tessellation Aspect of Combinational Cellular Array Testing · IEEE Trans. Computers 1974
Integrated circuit design › digital circuit design › logic array
cellular array design		 0.011976
Testable Sequential Cellular Arrays · IEEE Trans. Computers 1976
Electronic design automation › hardware verification and test
test generation		 0.011974
Tessellation Aspect of Combinational Cellular Array Testing · IEEE Trans. Computers 1974

Methods — techniques the papers use, named apart from their topics

testability conditions · 0.0prime tessellation · 0.0composite tessellation · 0.0
YearPublicationVenuePosition
1976 Testable Sequential Cellular Arrays
abstract
The progress of semiconductor technology has been a dominant factor on the use of cellular arrays in digital computer design. When a subsystem is implemented in the form of a cellular array, it is important that the subsystem can be tested at the array terminals for the presence of a faulty cell in the array. In this paper some sufficient conditions for the testability of two-dimensional sequential cellular arrays are derived. These can be either unilaterally interconnected or bilaterally interconnected arrays where each cell has some storage elements and logic circuits.
Chia-Hsiaing Sung
 IEEE Trans. Computers1
1974 Tessellation Aspect of Combinational Cellular Array Testing
abstract
This paper introduces procedures which enable one to settle the tessellation problem for the class of combinational cellular arrays with each cell having a binary horizontal input and a binary vertical input. Where all input combinations are applicable to all cells in the array in this class, the necessary number of tests is obtained from necessary prime as well as composite tessellations.
Chia-Hsiaing Sung, Clarence L. Coates
 IEEE Trans. Computers1