Timed Petri nets are convenient models of cluster tools as they represent the flow of wafers through the chambers of the tool as well as consecutive actions performed by the robotic transporter. Since the durations of all activities are also represented in such model, performance characteristics can be derived for steady-state as well as for transient behaviors. Steady-state performance of tools with chamber revisiting is investigated in this paper. A general description of cluster tools is proposed for systematic derivation of schedules, and a Petri net model is automatically derived from this description. The performance of the modeled system is derived by using place invariants, without exhaustive reachability analysis.

In fine-grain multithreading, the thread changes in each processor cycle, consecutive instructions are thus issued from different threads, and no data dependencies stall the pipeline. Enhanced fine-grain multithreading maintains a number of additional threads which are used to replace an active thread when it initiates a long-latency operation. Performance improvements due to enhanced multithreading are studied by analyzing a timed Petri net model of a fine-grain multithreaded architecture at the instruction execution level.

A systematic approach to modeling the stationary behavior of cluster tools by timed Petri nets is presented. The performance of the derived models is evaluated by structural methods (place invariants), without the exhaustive generation of the state space. Multiple robots are introduced to reduce the limitations of "transport bound" tools. Simple examples are provided to illustrate the proposed approach.

Timed Petri nets are used as models of cluster tools representing the flow of wafers through the chambers of the tool as well as sequences of actions performed by the robotic transporter. Since the durations of all activities are also represented in the model, performance characteristics can be derived from the model for steady-state, as well as transient behaviors. The performance of single-blade tools is compared with that of dual-blade tools. The effects of multiple loadlocks, redundant chambers and multiple robots are discussed and, analyzed. Modeling of wafer routings with chamber revisiting and processing of wafers of multiple types is also briefly discussed.

Hierarchical analysis of manufacturing systems is performed in a top-down manner in which a general, approximate model is used to capture the main effects of component interconnections, while more detailed models of components provide the detailed information needed for the derivation of performance characteristics of the entire system. For Petri net models, this approach corresponds to stepwise refinements of models. Structural analysis, based on place invariants combined with simple net transformations, is used to obtain performance characteristics of the modeled systems.

Timed Petri nets are used as models of cluster tools, representing not only the concurrent activities of different chambers, but also the durations of these activities. Structural analysis, based on net invariants, provides basic performance measures, such as throughput and cycle time. The results are obtained in symbolic form, so many specific alternatives can easily be compared without repeated analyses of the models.

Several simple applications of timed Petri nets to modeling and performance analysis of concurrent systems are presented as an illustration of a uniform approach to analysis of a wide class of discrete-event systems. Such a unified approach is used in a graduate course on performance evaluation of systems at Memorial University.

In distributed memory multithreaded systems, the long memory latencies and unpredictable synchronization delays are tolerated by context switching, i.e., by suspending the current thread and switching the processor to another thread waiting for execution. Simple analytical upper bounds on performance measures are derived using throughput analysis and extreme values of some model parameters. These derived bounds are compared with performance results obtained by simulation of a detailed model of the analyzed architecture.

Different types of applications of symbolic analysis in circuit design are considered regarding the most adequate form of symbolic results storage and manipulation. Different mathematical procedures are examined as a function of their efficiency. Polynomial and non-polynomial admittances are considered. Hierarchical and direct approaches are compared.

An interface to symbolic circuit analysis has been developed for a SPICE-like circuit simulator in order to integrate numerical simulation with an existing program for symbolic circuit analysis. In effect, both numerical and symbolic analyses use the same internal representation of circuits which makes the two approaches truly complementary. This integrated simulation capability is used in simulation-based parameter extraction where all AC small-signal parameters are fitted through the symbolic analysis rather than numerical one, significantly reducing the execution time of the extraction process.>

It is shown that the behavior of a certain class of timed Petri nets can be represented by a finite labeled directed graph in which the labels describe times and probabilities of transitions between vertices of the graph. Further analysis of such a graph can be done by techniques known for Markov chains. The method is applied to evaluation of some performance indices for two simple processor architectures. The timed Petri nets modeling the processors are shown and the resulting performance indices are compared. Some other architectures are discussed shortly.