This paper presents a System-on-a-Chip design methodology that uses a microprocessor subsystem as a building block for the development of chips for networking applications. The microprocessor subsystem is a self-contained macro that functions as an accelerator for computation-intensive pieces of the application code, and complements the standard components of the SoC. It consists of processor cores, memory banks, and well-defined interfaces that are interconnected via a high-performance switch. The number of processors and memory banks are parameters that can vary depending on the application to be implemented on the chip. Applications such as protocol conversion, TCP/IP off-load engine, or firewalls can be implemented with processor counts ranging from 8 to 128.

We have proposed and evaluated a scalable architecture for implementing multi-gigabit protocol engines. The architecture utilizes a combination of custom-made VLSI circuitry and a general-purpose processor, such as the Intel 960 or the IBM PowerPC 403. Time critical operations such as line coding/decoding, CRC generation/checking, context-independent header processing, and buffer management are implemented in the customized VLSI part. These designs are never-the-less scalable and can be cascaded to further increase throughput. Some of the packet level processing, such as context-dependent header processing, are performed by the general-purpose processor. As processing power increases, more and more functions can be included in the general purpose processor. The throughput of this architecture is shown to be adequate for the operations and bit rates currently specified by Fibre Channel. Future CMOS technology advances will have the potential to further improve the raw throughput.

The paper discusses a control scheme for broadband switching systems consisting of a hybrid multilevel control network and a three-phase commit control protocol. The proposed architecture and protocol allow for fast connection setup in point-to-point connections while efficiently handling multicast and broadcast connections. The consistency of system status is maintained through the three-phase commit procedure. The optimal control configuration to minimize the connection setup service time is derived by using both analytical and simulation approaches.

We describe a method of controlling a three-stage Clos nonblocking switch where "speculative" self-routing over the Clos fabric is augmented with reservations over a control network that connects controllers in the input and output stages of the switch. The effect is that most connections succeed over the speculative path while those subject to contention are processed over the control network. We present simulation result which indicate that the inclusion of a control network yields significant benefits under heavily nonuniform traffic conditions.

Optical metropolitan/wide area networks with arbitrary topology usually require optical amplifiers to compensate for the fiber attenuation and splitting loss introduced by the star couplers. An amplifier placement algorithm using spanning tree traversal is proposed. Using this algorithm, the authors show that it is possible to equalize the arriving optical signals at each receiver of the network. This technique enhances other static or dynamic gain equalization schemes and presents a more effective and robust solution to the power equalization problem for WDMA networks with arbitrary topology.>

A major impediment to building large crosspoint chips for configuring crosspoint switching networks is the simultaneous switching (Delta-I) noise problem that is caused by the switching of a large number of line drivers driving the output pins of the package. This limits the size of the largest crosspoint chips that can be operated reliably. An architectural solution to this problem is presented for networks constructed from one-sided crosspoint switching chips. The approach seeks to minimize the maximum number of active drivers in the individual chips by distributing the active drivers in the network uniformly among the chips by allowing rearrangements of existing connections when a new connection is made. A graph model is used to determine the number and location of rearrangements. An allocation scheme based on a simplified graph model that achieves a 50% reduction in the maximum number of active drivers per chip as compared to a random allocation strategy is presented. A maximum of three rearrangements is sufficient to obtain this reduction.>

In this paper we describe an experimental coprocessor for an IBM 4381 that is designed to facilitate the exploration of persistent objects.