Prashant Agrawal

dblp:20/3423 · DBLP profile ↗
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15ranked-venue papers
6as first author
3since 2021 · last 2026
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 9 · 3 first-authorComputer networks · 2 · 1 first-authorSecurity and privacy · 2 · 2 first-author · 2 since 2021Software engineering, systems software and programming languages · 1Databases, data management, data science and information retrieval · 1 · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021
YearPublicationVenuePosition
2026 YouChoose: A Lightweight Anonymous Proof of Account Ownership
abstract
Anonymous proofs of account ownership (anonymous PAOs) enable a prover to convince a verifier that the prover owns a valid account at a server without revealing their identity. Importantly, no server-side changes are required - the server does not even learn that such a proof is taking place. This functionality is particularly valuable in sensitive applications such as whistleblowing, or in settings where infrastructural changes at the server are impractical. Anonymous PAOs were first introduced by Wang et al. (IEEE S&P 2019), who realized them in the email setting via secure channel injection (SCI), a technique that requires carefully engineered multi-party computation (MPC) protocols. In this work, we propose YouChoose, a new approach to anonymous PAO that avoids MPC entirely, relying instead on the verifier to selectively forward TLS records. Compared to SCI, YouChoose is simpler, faster, and more adaptable across services. We also provide the first formal security definition for anonymous PAOs, establishing a rigorous framework for analysis and future constructions. Finally, we present a prototype implementation of YouChoose, evaluate it in the context of email and other social media accounts, showing its better performance than SCI with minimal latency overhead in practice.
Aarav Varshney, Prashant Agrawal, Mahabir Prasad Jhanwar
WWW2
2024 Publicly Auditable Privacy-Preserving Electoral Rolls
abstract
While existing literature on electronic voting has extensively addressed verifiability of voting protocols, the vulnerability of electoral rolls in large public elections remains a critical concern. To ensure integrity of electoral rolls, the current practice is to either make electoral rolls public or share them with the political parties. However, this enables construction of detailed voter profiles and selective targeting and manipulation of voters, thereby undermining the fundamental principle of free and fair elections. In this paper, we study the problem of designing publicly auditable yet privacy-preserving electoral rolls. We first formulate a threat model and provide formal security definitions. We then present a protocol for creation, maintenance and usage of electoral rolls that mitigates the threats. Eligible voters can verify their inclusion, whereas political parties and auditors can statistically audit the electoral roll. Further, the audit can also detect polling-day ballot stuffing and denials to eligible voters by malicious polling officers. The entire electoral roll is never revealed, which prevents any large-scale systematic voter targeting and manipulation.
Prashant Agrawal, Mahabir Prasad Jhanwar, Subodh Sharma 0001, Subhashis Banerjee
CSF1
2024 Traceable mixnets
abstract
We introduce the notion of traceable mixnets. In a traditional mixnet, multiple mix-servers jointly permute and decrypt a list of ciphertexts to produce a list of plaintexts, along with a proof of correctness, such that the association between individual ciphertexts and plaintexts remains completely hidden. However, in many applications, the privacy-utility tradeoff requires answering some specific queries about this association, without revealing any information beyond the query result. We consider queries of the following types: a) given a ciphertext in the mixnet input list, whether it encrypts one of a given subset of plaintexts in the output list, and b) given a plaintext in the mixnet output list, whether it is a decryption of one of a given subset of ciphertexts in the input list. Traceable mixnets allow the mix-servers to jointly prove answers to the above queries to a querier such that neither the querier nor a threshold number of mix-servers learn any information beyond the query result. Further, if the querier is not corrupted, the corrupted mix-servers do not even learn the query result. We first comprehensively formalise these security properties of traceable mixnets and then propose a construction of traceable mixnets using novel distributed zero-knowledge proofs (ZKPs) of set membership and of a statement we call reverse set membership. Although set membership has been studied in the single-prover setting, the main challenge in our distributed setting lies in making sure that none of the mix-servers learn the association between ciphertexts and plaintexts during the proof. We implement our distributed ZKPs and show that they are faster than state-of-the-art by at least one order of magnitude.
Prashant Agrawal, Abhinav Nakarmi, Mahabir Prasad Jhanwar, Subodh Sharma 0001, Subhashis Banerjee
Proc. Priv. Enhancing Technol.1
2016 Data Flow Transformation for Energy-Efficient Implementation of Givens Rotation-Based QRD
abstract
QR decomposition (QRD), a matrix decomposition algorithm widely used in embedded application domain, can be realized in a large number of valid processing sequences that differ significantly in the number of memory accesses and computations, and hence the overall implementation energy. With modern low-power embedded processors evolving toward register files with wide memory interfaces and vector functional units (FUs), data flow in these algorithms needs to be carefully devised to efficiently utilize the costly wide memory accesses and the vector FUs. In this article, we present an energy-efficient data flow transformation strategy for the Givens rotation--based QRD.
Namita Sharma 0001, Preeti Ranjan Panda, Francky Catthoor, Min Li 0001, Prashant Agrawal
ACM Trans. Embed. Comput. Syst.5
2014 Energy efficient data flow transformation for Givens Rotation based QR Decomposition
abstract
QR Decomposition (QRD) is a typical matrix decomposition algorithm that shares many common features with other algorithms such as LU and Cholesky decomposition. The principle can be realized in a large number of valid processing sequences that differ significantly in the number of memory accesses and computations, and hence, the overall implementation energy. With modern low power embedded processors evolving towards register files with wide memory interfaces and vector functional units (FUs), the data flow in matrix decomposition algorithms needs to be carefully devised to achieve energy efficient implementation. In this paper, we present an efficient data flow transformation strategy for the Givens Rotation based QRD that optimizes data memory accesses. We also explore different possible implementations for QRD of multiple matrices using the SIMD feature of the processor. With the proposed data flow transformation, a reduction of up to 36% is achieved in the overall energy over conventional QRD sequences.
Namita Sharma 0001, Preeti Ranjan Panda, Min Li 0001, Prashant Agrawal, Francky Catthoor
DATE4
2014 Modelling and mitigation of time-zero variability in sub-16nm finfet-based STT-MRAM memories
abstract
Spin-transfer torque magnetic RAM (STT-MRAM) is one of the most promising non-volatile memory technologies and shows potential as an SRAM replacement. However, targeted for advanced CMOS technologies such as the 14nm FinFET node, time-zero variability is a major concern for these memory technologies. In this paper, we investigate the STT-MRAM variability with respect to different technology scenarios. We show the impact of these variations on the bit error rate of the emerging STT-MRAM memories.
Matthias Hartmann, Halil Kukner, Prashant Agrawal, Praveen Raghavan, Liesbet Van der Perre, Wim Dehaene
ACM Great Lakes Symposium on VLSI3
2013 Early exploration for platform architecture instantiation with multi-mode application partitioning
abstract
We present a systematic methodology for exploring application partitioning and assignment together with platform architecture instantiation. Streaming applications with multiple runtime modes are considered. The platform architecture is based on a domain specific MPSoC architecture template. We show results using complete inner modem physical layer processing of wireless applications, WLAN and LTE. We show that the proposed methodology obtains up to 30% energy improvement in energy with negligible area overheads as compared to straight-forward mapping to one processor, while meeting performance constraints, for a multi-mode WLAN 11n system and single-mode LTE system.
Prashant Agrawal, Praveen Raghavan, Matthias Hartmann, Namita Sharma 0001, Liesbet Van der Perre, Francky Catthoor
DAC1
2013 Memristor-Based (ReRAM) Data Memory Architecture in ASIP Design
abstract
Recently, multiple non-volatile emerging memories (NVMs) have been proposed and show promising properties to replace SRAM-based memories in future SoCs. However, these new emerging memories, such as STT-MRAM and ReRAM, provide new challenges for the processor design e.g. larger write latencies, higher power and lower endurance. In this paper, we propose a design method for memristor-based (ReRAM) memory architectures for embedded processors to address the effects caused by longer write latencies. We evaluate this method and present the design space for using ReRAM in the data memory of an wireless base band processor. We propose architectural solutions for concealing the slow write speed of ReRAM and show their trade-offs in terms of performance with respect to different write latencies. We show that for single benchmarks the performance penalty caused by the ReRAM write latency can be reduced to 7% for the complete wireless communication benchmark suite. Morevoer, for single benchmarks the performance penalty can be eliminated completely.
Matthias Hartmann, Praveen Raghavan, Liesbet Van der Perre, Prashant Agrawal, Wim Dehaene
DSD4
2013 Data memory optimization in LTE downlink
abstract
Optimizations related to memory accesses and data storage make a significant difference to the performance and energy of a wide range of data-intensive applications. Such strategies need to evolve with modern SoC and processor architectures, which lead to new optimization opportunities. In this paper, we focus on data memory optimization for LTE downlink receiver as this is a data- and computation-intensive part of the LTE application with tight energy and latency constraints. We study the data dependencies globally and conclude that by providing data samples from the antennas in interleaved form at the FFT input, we can achieve 7-15% reduction in memory access energy over an optimized implementation without any performance overhead.
Namita Sharma 0001, Tom Vander Aa, Prashant Agrawal, Praveen Raghavan, Preeti Ranjan Panda, Francky Catthoor
ICASSP3
2012 Partitioning and Assignment Exploration for Multiple Modes of IEEE 802.11n Modem on Heterogeneous MPSoC Platforms
abstract
With the advent of heterogeneous MPSoC platform architecture based implementations for the IEEE 802.11n PHY processing, system partitioning and assignment (P&A) have become a key challenge. In this paper we have analyzed the area and energy trade-offs across different P&A schemes for the 4×4 and the 2×2 MIMO 40MHz modes of 802.11n. We have considered the payload processing part of the inner-modem processing for 802.11n PHY. We also present a framework for systematically carrying out the P&A exploration. We show that by exploiting parallelism at different levels, the energy can be reduced with negligible area overheads, by about 40% and 15% for the 4×4 and 2×2 modes, respectively. We also show that the P&A schemes with fine-grained partitioning are more energy efficient for mapping both the modes together on the same platform.
Prashant Agrawal, Kanishk Sugand, Martin Palkovic, Praveen Raghavan, Liesbet Van der Perre, Francky Catthoor
DSD1
2009 Performance optimizations for distributed real-time text indexing
abstract
DISC (Data-Intensive Super Computing) is gaining strong research momentum [1]. DISC systems differ from conventional supercomputers in their focus on data, as they acquire and maintain continually changing massive data sets, in addition to performing large-scale computations over the data. Towards this end, we consider the problem of real-time text indexing and search with high input data rates (10 GB/s or more) along with small index age-off time while sustaining search response time. Load imbalance and communication bottlenecks make this problem particularly challenging. We present performance optimizations for distributed in-memory text indexing of massive input data sets on parallel systems having large number of cores/processors, with sustained search performance [2]. Our distributed indexing algorithm uses a hybrid group-based approach which enables scalable indexing and search over massively parallel systems. In addition, we designed and analyzed communication optimizations including routing using Steiner nodes and topology mapping. Using theoretical analysis for the asymptotic parallel time complexity we establish the scalability of our algorithm with |P| for small index-group size and scalability with |C| for larger index-group size; where |P| and |C| are the number of Producers and Consumers respectively, in the index-group. We have obtained indexing throughput of 524 GB/min on 4K nodes of Blue Gene/L1using actual IBM intranet data, which is 3.36x better than the previous best throughput [3] and 10.3x better than typical indexing approaches such as CLucene2on the same number of nodes. This gives an estimated throughput of 17 TB/min on 128K nodes with sustained search performance. We also demonstrate the improvements in strong and weak scalability of our distributed indexing algorithm over the previous best [3] on Blue Gene/L. To the best of our knowledge, this is the highest indexing throughput ever published on a large scale system with sustained search performance.
Ankur Narang, Karthik Swaminathan, Prashant Agrawal
HiPC3
2008 Optimization of BLAS on the Cell Processor
Vaibhav Saxena, Prashant Agrawal, Yogish Sabharwal, Vijay K. Garg, Vimitha A. Kuruvilla, John A. Gunnels
HiPC2
2007 A path based modeling approach for dynamic power estimation
abstract
In this paper a path based modeling approach due to different internal traffic scenarios is proposed for dynamic power estimation, under Thermal Design Power (TDP) conditions, for data path intensive designs. The model estimates power as a function of bandwidth and effective toggle rate of the input data transactions. It also takes into account the effect of cross-coupling capacitance on dynamic power. The model scales well to obtain power estimates for a design which is a proliferation of the existing one. This enables to get an early power estimation for a next generation design. The effectiveness of the proposed modeling approach has been demonstrated on a complex industrial design.
Prashant Agrawal, R. Srinivasa, Ajit N. Oke, Saurabh Vijay
ACM Great Lakes Symposium on VLSI1
2005 Effect of routing convergence time on lightpath establishment in GMPLS-controlled WDM optical networks
abstract
In this paper we consider routing and wavelength assignment of primary and shared backup lightpaths using OSPF-TE routing information and CR-LDP signalling in GMPLS-based WDM optical mesh networks. In the emerging generalized multi-protocol label switching (GMPLS) based WDM transport networks, called intelligent optical transport networks, WDM-based optical components like add-drop multiplexers (ADMs) and optical cross connects (OXCs) will have full knowledge of the wavelengths in the network, status, and traffic carrying capacity of each wavelength. With such intelligence, these intelligent optical networks could create self-connecting and self-regulating connections on-the-fly. In these networks, after a lightpath establishment or release, the routing protocol may take considerable amount of time to update the routing database at all the nodes in the network, known as routing convergence time (T/sub o/). In case of dynamic traffic, where lightpath requests arrive to and depart from the network randomly; the routing and wavelength assignment for a new lightpath request may be carried out based on non-updated (old) link state information resulting in conflicts and hence leads to higher blocking probability. In this paper we evaluate the blocking performance for different scenarios, such as primary and shared backup lightpath establishment, with full and partial information. The simulation results show that the partial information case over performs the full information case with respect to connection blocking probability.
Luying Zhou, Prashant Agrawal, Chava Vijaya Saradhi, Victor Foo Siang Fook
ICC2
2003 A lightweight protocol for wireless sensor networks
abstract
Wireless sensor networks are widely used in data acquisition frameworks. Unlike conventional networked devices, wireless sensors run on low power energy sources, and have limited memory buffers, minimal computational complexity, and low processing speeds. As such, the complexities involved with conventional network protocols cannot be realized in wireless sensors. A data dissemination protocol for wireless sensor network should be well aware of sensor limitations. In addition, it should also take into consideration, the unique aspects of applications running over wireless sensor networks. In this paper, we propose a new network protocol, Simple Wireless Sensor Protocol (SWSP) for wireless sensors which provides a reliable data communication between wireless sensors with minimum resource overhead.
Prashant Agrawal, Tan Sun Teck, Akkihebbal L. Ananda
WCNC1