We have developed a quarter video graphics array (QVGA) chip for full-digital image sensing by using three-dimensional (3D) integration technology. In-pixel pulse-frequency modulation (PFM) analog-to-digital converter (ADC) gives full-digital imaging pixel, which is known to overcome signal saturation due to the full well capacity of a photodiode (PD). We have also newly designed a PFM-ADC for pixels with a pinned PD and a floating diffusion to achieve high sensitivity and low noise. PDs and ADCs were stacked into two layers by pixel-wise 3D integration with gold electrodes of 5 μm in diameter, thereby enabling QVGA resolution for a 20-mm square chip in 0.18-μm and 0.2-μm process nodes. The developed sensor chip exhibited an excellent linearity and wide dynamic range of more than 96 dB. We also obtained video images with a high bit depth of 16 bit, demonstrating the superior image sensing that can capture the real world at high fidelity.

This special issue presents a variety of invited papers covering nanostructures and related materials proposed to extend CMOS scaling to its ultimate limit and enable a variety of new logic and memory devices.

This paper will outline some results obtained by an international working group on nanoelectronics, which collects data from major publicly funded programs in Europe, Japan, and the United States on long-term nanoelectronics research. It maps these programs and projects onto a set of research directions that are expected to drive nanoelectronics for the long term. The purpose is to identify those research topics attracting a lot of attention and those important topics that seem less attractive. This paper will give examples of interregional collaborative programs and identify sources of funding specifically provided to support international collaborations.

A compact analytical model of variable-threshold-voltage CMOS (VTCMOS) is proposed to study the active on current, linking it with the standby off-current characteristics. Comparisons of modeled results to both numerical simulations and experimental data are made with an excellent agreement. It is clearly demonstrated using the model that speed degradation due to low supply voltage can be compensated by the VTCMOS scheme, even with smaller power. Influence of the short channel effect (SCE) on the performance of VTCMOS is investigated in terms of a new parameter, dS/d/spl gamma/, both qualitatively and quantitatively. It is found that the SCE degrades the VTCMOS performance. Issues on the optimum conditions of VTCMOS and the performance of series-connected VTCMOS circuits are also discussed.

A very compact analytical model of variable threshold voltage CMOS (VTCMOS) is proposed to study the active on-current, linking it with the stand-by off-current characteristics. Comparisons of modeled results to numerical simulations and experimental data are made with an excellent agreement. It is clearly demonstrated using the model that speed degradation due to low supply voltage can be compensated by the VTCMOS scheme with even smaller power. Influence of the short channel effect (SCE) on the performance of VTCMOS is investigated in terms of a new parameter, dS/dγ, both qualitatively and quantitatively. It is found that the SCE degrades the VTCMOS performance. Issues on the optimum conditions of VTCMOS are discussed.

Article Share on Variable threshold CMOS (VTCMOS) in series connected circuits Authors: Takashi Inukai Institute of Industrial Science, University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japan Institute of Industrial Science, University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, JapanView Profile , Toshiro Hiramoto Institute of Industrial Science, University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japan and VLSI Design and Education Center, University of Tokyo Institute of Industrial Science, University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japan and VLSI Design and Education Center, University of TokyoView Profile , Takayasu Sakurai Institute of Industrial Science, University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japan and Center for Collaborative Research, University of Tokyo Institute of Industrial Science, University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japan and Center for Collaborative Research, University of TokyoView Profile Authors Info & Claims ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and designAugust 2001Pages 201–206https://doi.org/10.1145/383082.383133Published:06 August 2001Publication History 10citation398DownloadsMetricsTotal Citations10Total Downloads398Last 12 Months3Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access