This work introduces SENSOTERIC, a multi-partner project that aims at leveraging the properties of emerging Reconfigurable Field Effect Transistors (RFETs) to develop a sensor platform. RFETs will be used for a generic sensor interface and for a dedicated transducer element. In the first case, our goal is to develop an analog front-end interface that can be tuned at runtime to adapt to different environmental conditions and be used in a broad spectrum of applications. This feature shall be enabled by the polarity-control and negative differential resistance characteristics of the reconfigurable devices employed, that are co-integrable on industrial CMOS processes such as 22 nm FDSOI. In the second case, we want to exploit the intrinsic nature of these doping-free devices to yield better 1/f noise performances when compared to classic CMOS transducers. Moreover, the presence of un-gated areas on top of the channel of these devices makes them the perfect candidates to be functionalized. In this early-stage overview of the project, we will introduce the key features and the vision that make SENSOTERIC a unique contribution towards smart sensing solutions in environmental monitoring and healthcare.

This multi-partner-project contribution introduces the midway results of the Horizon 2020 FVLLMONTI project. In this project we develop a new and ultra-efficient class of ANN accelerators, the neural network compute cube$(N^{2}C^{2})$, which is specifically designed to execute complex machine learning tasks in a 3D technology, in order to provide the high computing power and ultra-high efficiency needed for future edgeAI applications. We showcase its effectiveness by targeting the challenging class of Transformer ANNs, tailored for Automatic Speech Recognition and Machine Translation, the two fundamental components of speech-to-speech translation. To gain the full benefit of the accelerator design, we develop disruptive vertical transistor technologies and execute design-technology-co-optimization (DTCO) loops from single device, to cell and compute cube level. Further, a hardware-software-co-optimization is executed, e.g. by compressing the executed speech recognition and translation models for energy efficient executing without substantial loss in precision.

InP double heterojunction bipolar transistors (InP DHBTs) are one of the key technologies considered for terahertz (THz) applications. The improvement of their frequency performance is challenging and strongly dependent on various parameters (manufacturing process, geometry, and epitaxial structure). In this article, a novel method is developed to take into account these parameters and predict the frequency performance of the technology. This approach consists of rebuilding the S-parameter matrix of the small-signal model. Elements of the small signal model are identified, and their assessment is described in detail. Once calibrated with the present state-of-the-art device features, the model shows a good agreement with the measurements. Based on this result, analysis of the emitter and base technological features are performed along with optimizations of the vertical structure. Finally, the necessary optimizations for developing a THz transistor are detailed. This works provides guidelines for technological improvement and opens the way for designing transistors operating at frequencies above a THz.

This article reports the first accurate and physics-based Verilog-A implementation of the fully analytic form of photocurrent in SPICE compact models for uni-traveling carrier (UTC) photodiodes (PDs). To overcome the limitations of single-pole network implementations for modeling frequency dependence of the photo-response, especially at frequencies beyond 100 GHz, we explored different solutions for the complete analytic equation of the dynamic photocurrent. A new implementation has been proposed which requires three additional nodes in the UTC-PD electrical equivalent circuit and offers the best tradeoff between accuracy and computational efficiency. Model validation has been performed against on-wafer measurements from two UTC-PD technologies depicting very good accuracy over the entire frequency range.

Vertical Nanowire Junction-less Transistors (VN-WFET) are a promising technology for designing energy-efficient neural networks. This work presents the first results for 3D VNWFET logic cell design taking into account the influence of intra-cell parasitic interconnects on circuit performances. The proposed methodology is used to investigate the performance of a CMOS inverter through co-simulation of the VNWFET SPICE compact model coupled with the circuit parasitic netlist extracted from 3D TCAD simulations using a standard circuit simulator.

Bias temperature instability (BTI) and hot carrier injection (HCI) are both prominent reliability concerns for integrated circuits (ICs). In this paper, we investigated these failure mechanisms on 0.18μm CMOS (Complementary Metal-Oxide-Semiconductor) submitted to severe temperatures (150°C and 210°C) for long period of stress (up to 2,000 hours). Additionally, the transistors were applied dedicated stress conditions to activate the intrinsic HCI and BTI wear-out mechanisms. The aging laws were proposed based on these experimental results and implemented into the commercial software tool for further investigation at logic circuit level.

Gate-all-around Vertical Nanowire Field Effect Transistors (VNWFET) are emerging devices., which are well suited to pursue scaling beyond lateral scaling limitations around 7nm. This work explores the relative merits and drawbacks of the technology in the context of logic cell design. We describe a junctionless nanowire technology and associated compact model., which accurately describes fabricated device behavior in all regions of operations for transistors based on between 16 and 625 parallel nanowires of diameters between 22 and 50nm. We used this model to simulate the projected performance of inverter logic gates based on passive load., active load and complementary topologies and carry out an performance exploration for the number of nanowires in transistors. In terms of compactness., through a dedicated full 3D layout design., we also demonstrate a 48% reduction in lateral dimensions for the complementary structure with respect to 7nm FinFET-based inverters.

This paper presents Si/SiGe:C and InP/GaAsSb HBTs which feature specific assets to address submillimeter-wave and THz applications. Process and modeling status and challenges are reviewed. The specific topics of thermal and substrate effects, reliability, and HF measurements are also discussed.

This letter presents the characterisation of a GFET transistor with a source-pull/load-pull test bench. The characterisation shows that despite the good fTand fMAX, it is hard to achieve reasonable power gain using the GFET device in a circuit configuration. This is due to the very high impedance at the gate making impedance matching at the input extremely difficult. An electrical model is used to evaluate the optimum power gain of the transistor under matched conditions. In a second part, a benchmarking of the technology is realized through accurate simulation of an optimised GFET device. Based on this input data, a compact model permits the evaluation of the GFET for high frequency amplifications.