Abstract Fully homomorphic encryption (FHE) has emerged as a prominent area of cryptographic research in recent years, offering the capability to perform computations on ciphertext without compromising data privacy. Among various FHE schemes, the Cheon–Kim–Kim–Song (CKKS) algorithm for approximate homomorphic encryption has gained prominence due to its efficient handling of floating-point operations. Bootstrapping, a critical technique that enables unlimited homomorphic operations by refreshing noisy ciphertexts, represents both the most complex and essential component of practical FHE implementations. This survey provides a comprehensive analysis of bootstrapping techniques in CKKS, examining their evolution from the original proposal to current state-of-the-art methods. Recent literature has witnessed a proliferation of novel bootstrapping schemes for CKKS, these diverse approaches often emphasize different performance aspects, leading to a lack of a unified quantitative framework for comparative analysis. To address this gap, we systematically categorize existing approaches into three main directions: optimization of homomorphic modular reduction, optimization of encoding/decoding operations, and development of alternative constructions using blind rotation techniques. Through detailed comparative analysis, we identify that current schemes can achieve either high throughput (processing over 1000 ciphertexts per second) or high precision (up to 400 bits), but exhibit limitations in concurrent optimization of both parameters. Furthermore, potential directions for future optimizations are explored and discussed, contributing to the ongoing development of efficient and practical FHE systems.

Private data alignment, as the prerequisite for multiparty collaborative computation, attracts more attention in recent years, and some existing researches achieve the intersection sharing through two-party private set intersection (PSI) protocol based on various cryptographic techniques. However, they focus on the correctness and confidentiality of the protocol in the two-party scenario, while ignoring the efficiency and scalability in multiparty scenario. Additionally, the multiparty PSI protocol is difficult to be compatible with two parties simultaneously. To this end, we propose an oblivious pseudorandom function-based PSI scheme to achieve the data alignment, which is suitable for two parties and multiple parties. Specifically, to avoid frequent interactions among multiple parties, an efficient filtering algorithm is designed with the assistance of a server. The security proof for semi-honest and corrupted parties is provided, meanwhile, the computation and communication overhead analysis is given in detail. To evaluate the performance, we deploy the proposed scheme in two-party and multiparty scenario, and compare it with the existing protocols to discuss the execution complexity and overhead, which shows the efficiency and scalability of the proposed scheme in the multiparty scenario.

Private set intersection (PSI) has emerged as a key cryptographic protocol, enabling secure data sharing and facilitating collaborative computing among distributed data providers in recent years. However, it remains challenging to achieve efficient multiparty private set intersection (MPSI) for large-scale data and numerous participants in an open environment. To this end, we propose EL-MPSI, an Efficient and Lightweight MPSI scheme based on Vector Oblivious Linear Evaluation (VOLE) and Oblivious Key-Value Store (OKVS), which enables secure data sharing in settings with millions of datasets and dozens of participants. By simplifying the interaction process among multiple participants, the proposed scheme achieves constant-level round complexity and provides resistance against malicious adversaries, as well as collusion attack. Through theoretical analysis and experiments, we demonstrate that the security, efficiency and scalability of our scheme perform better than existing state-of-the-art (SOTA) works. For millions of datasets and dozens of participants, EL-MPSI achieves second-level latency while keeping client communication overhead to approximately 10 MB. Moreover, in scenarios of malicious adversary setting, the extra execution overhead is negligible, which effectively facilitates large-scale data sharing.

Federated Learning (FL) has attracted increasing attention from both academia and industry due to its merit of securely constructing AI models across multiple entities while preserving the privacy of local training data. However, recent research shows two persisting problems in FL that have yet to be solved: (1) limited practical adaptation of federated learning because of time-consuming conventional privacy-preserving methods, and (2) the absence of quantum-computing resistance in these methods. To address these problems, we propose a novel vertical federated learning strategy, HQsFL, which relies on Fully Homomorphic Encryption (FHE) and Matrix Vector Product basing on Coefficient Encoding. The proposed method can be widely applied to FL algorithms such as logistic regression and XGBoost, etc. We fully implement our approach and evaluate its utility and efficiency through extensive experiments performed on four synthetic datasets. The experimental results demonstrate that our proposed methods for vertical LR and XGBoost achieve comparable levels of AUC to conventional methods, while significantly improving training efficiency and achieving security property of quantum-computing resistance.

Persistent fault analysis (PFA) is a newly proposed cryptanalysis for block ciphers. Although the injected fault is persistent during the entire encryption, the corresponding analysis is only applied to the last round in the original PFA. In this article, the enhanced PFA (EPFA) is proposed, which can push the limit of PFA by exploiting the fault leakage in deeper rounds and target to reduce the number of required ciphertexts as small as possible. EPFA is first introduced as a general method with a specific application to advanced encryption standard (AES). Then it is extended to other substitution–permutation network (SPN)-based block ciphers, such as LED and SKINNY, both of which have unique features that EPFA fits well. To improve the efficiency of EPFA, a parallel algorithm based on mixed radix numbers is developed, which fully utilizes the power of GPU. Our experimental results show that EPFA can reduce the number of required ciphertexts to be under 1000, which is only about 40% of the 2500 ciphertexts in previous PFA on AES. In contrast to the single-threaded implementation, the parallel EPFA can have a speedup roughly about 200 times.

The implementations of post-quantum cryptographic algorithms have been newly explored, whereas, the protection against side-channel attacks shall be considered upfront, since it can have a non-negligible impact on security and performance. In this article, the security of supersingular isogeny key encapsulation (SIKE), a second-round candidate of NIST's on-going post-quantum standardization process, is thoroughly evaluated under side-channel analysis. First, the vulnerabilities of reference and optimized implementations of SIKE are thoroughly analyzed in terms of both horizontal and vertical side-channel leakage. After the optimized SIKE, which is based on Three-point Montgomery Differential Ladder algorithm, is proved to be constant-time and there is no horizontal leakage, a vertical vulnerability is analyzed based on the source code at the algorithmic level, and a theoretical differential power analysis (DPA) attack is proposed. In order to exploit this vulnerability, the differential electromagnetic attack (DEMA) is put into practice to extract the private key of SIKE based on a 32-bit ARM platform. To the best of our knowledge, this is the first practical side-channel attack at SIKE implemented on real ARM-based devices. Our experiments show that the DEMA needs only hundreds of electromagnetic traces to carry out the attack. More importantly, an efficient window-based countermeasure is proposed to eliminate the vertical leakage and prevent side-channel attacks with only a little overhead. The security of our countermeasure is carefully evaluated against most of well-known power analysis attacks. Through careful evaluation and comparison with other countermeasures, this method can lead to higher security at a very small cost in terms of time and memory.

Laser based Fault Injection (LFI) and Electromagnetic Fault Injection (EMFI) are powerful techniques commonly for fault injection against security critical circuits. Since LFI/EMFI creates faults by incurring high energy disturbances, they can be detected in advance by sensing the disturbance using a embedded detector. In this paper, a PLL based sensor system for detecting laser fault injection is presented. Experiments show a high detection rate, with significant power security margin, whilst maintaining low hardware cost, on multiple FPGA platforms.

HIGHT is a lightweight block cipher which has been adopted as a standard block cipher. In this paper, we present a bit-level algebraic fault analysis (AFA) of HIGHT, where the faults are perturbed by a stealthy HT. The fault model in our attack assumes that the adversary is able to insert a HT that flips a specific bit of a certain intermediate word of the cipher once the HT is activated. The HT is realized by merely 4 registers and with an extremely low activation rate of about 0.000025. We show that the optimal location for inserting the designed HT can be efficiently determined by AFA in advance. Finally, a method is proposed to represent the cipher and the injected faults with a merged set of algebraic equations and the master key can be recovered by solving the merged equation system with an SAT solver. Our attack, which fully recovers the secret master key of the cipher in 12572.26 seconds, requires three times of activation on the designed HT. To the best of our knowledge, this is the first Trojan attack on HIGHT.

Hardware Trojan (HT) has recently drawn much attention in both industry and academia due to the global outsourcing trend in semiconductor manufacturing, where a malicious logic can be inserted into the security critical ICs at almost any stages. HT severity mainly stems from its low-cost and stealthy nature where the HT only functions at a strict condition to purposely alter the logic or physical behavior for leaking secrets. This fact makes HT detection very challenging in practice. In this paper, we propose a novel HT detection technique based on machine learning approach. The described solution is constructed over one-class SVM and is shown to be more robust compared to the template based detection techniques. An unsupervised approach is also applied in our solution for mitigating the golden model dependencies. To evaluate the solution, a practical HT design was inserted into an AES coprocessor implemented in a Xilinx FPGA. Based on the partial reconfiguration, the HT size can be dynamically changed without altering cipher part, which helps to precisely evaluate the HT influence. The experimental results have shown that our proposed detection technique achieve a high performance accuracy.

Electromagnetic injection (EMI) is a powerful and precise technique for fault injection in modern ICs. This intentional fault can be utilized to steal secret information hidden inside of ICs. Unlike laser fault injection, tedious package decapsulation is not needed for EMI, which reduces an attacker's cost and thus causes a serious information security threat. In this paper, a PLL-based sensor circuit is proposed to detect EMI reactively on chip. A fully automatic design flow is devised to integrate the proposed sensor together with a cryptographic processor. A high fault detection coverage and a small hardware overhead are demonstrated experimentally on an FPGA platform.

As a typical semi-invasive attack against cryptographic primitives, laser fault injection (LFI) has emerged as a serious threat for security ICs. However, very few countermeasures against LFI have been proposed in previous literature. In this paper, a logic-level countermeasure for sensing the malicious laser injection on FPGA is presented. The implemented logic consists of a digital inverter ring oscillator (RO) for detecting the frequency disturbance by laser, and a Phase Locked Loop (PLL) to monitor the frequency ripple in RO, for generating an 'alarm' signal. The effectiveness of this countermeasure is validated by a series of laser scan on Xilinx Virtex-5 FPGA. The experimental results show that the detection rate reaches up to 92.82% for protecting the registers in slice, and the countermeasure offers a significant security margin against LFIs.

The security of the implemented cryptographic module in hardware has seen severe vulnerabilities against Side-Channel Attack (SCA), which is capable of retrieving hidden things by observing the pattern or quantity of unintentional information leakage. Dual-rail Precharge Logic (DPL) theoretically thwarts side-channel analyses by its low-level compensation manner, while the security reliability of DPLs can only be achieved at high resource expenses and degraded performance. In this paper, we present a dynamic protection system for selectively configuring the security-sensitive crypto modules to SCA-resistant dual-rail style in the scenario that the real-time threat is detected. The threat-response mechanism helps to dynamically balance the security and cost. The system is driven by a set of automated dual-rail conversion APIs for partially transforming the cryptographic module into its dual-rail format, particularly to a highly secure symmetric and interleaved placement. The elevated security grade from the safe to threat mode is validated by EM based mutual information analysis using fine-grained surface scan to a decapsulated Virtex-5 FPGA on SASEBO GII board.

Conventional dual‐rail precharge logic suffers from difficult implementations of dual‐rail structure for obtaining strict compensation between the counterpart rails. As a light‐weight and high‐speed dual‐rail style, balanced cell‐based dual‐rail logic (BCDL) uses synchronised compound gates with global precharge signal to provide high resistance against differential power or electromagnetic analyses. BCDL can be realised from generic field programmable gate array (FPGA) design flows with constraints. However, routings still exist as concerns because of the deficient flexibility on routing control, which unfavourably results in bias between complementary nets in security‐sensitive parts. In this article, based on a routing repair technique, novel verifications towards routing effect are presented. An 8 bit simplified advanced encryption processing (AES)‐co‐processor is executed that is constructed on block random access memory (RAM)‐based BCDL in Xilinx Virtex‐5 FPGAs. Since imbalanced routing are major defects in BCDL, the authors can rule out other influences and fairly quantify the security variants. A series of asymptotic correlation electromagnetic (EM) analyses are launched towards a group of circuits with consecutive routing schemes to be able to verify routing impact on side channel analyses. After repairing the non‐identical routings, Mutual information analyses are executed to further validate the concrete security increase obtained from identical routing pairs in BCDL.

Modern field programmable gate arrays (FPGAs) are power packed with features to facilitate designers. Availability of features like large block memory (BRAM), digital signal processing cores, and embedded CPU makes the design strategy of FPGAs quite different from ASICs. FPGAs are also widely used in security-critical applications where protection against known attacks is of prime importance. We focus on physical attacks that target physical implementations. To design countermeasures against such attacks, the strategy for FPGA designers should be different from that in ASIC. The available features should be exploited to design compact and strong countermeasures. In this article, we propose methods to exploit the BRAMs in FPGAs for designing compact countermeasures. Internal BRAM can be used to optimize intrinsic countermeasures such as masking and dual-rail logics, which otherwise have significant overhead (at least 2 × ) compared to unprotected ones. The optimizations are applied on a real AES-128 co-processor and tested for area overhead and resistance on Xilinx Virtex-5 chips. The presented masking countermeasure has an overhead of only 16% when applied on AES. Moreover, the dual-rail precharge logic (DPL) countermeasure has been optimized to pack the whole sequential part in the BRAM, hence enhancing the security. Proper robustness evaluations are conducted to analyze the optimization in terms of area and security.