Prebond testing of through-silicon-vias (TSVs) and die logic is a significant challenge and a potential roadblock for 3-D integration. Built-in self-test solutions introduce considerable die area overhead. Oversized probe pads on TSVs to provide prebond test access limit both test bandwidth and TSV density. This paper presents a solution to these problems, allowing a probe card to contact TSVs without the need for probe pads, enabling both TSV and prebond scan test. Several possible prebond scan test configurations are shown-they provide varying degrees of test parallelism under design constraints. HSPICE simulations are performed on two logic-on-logic 3-D benchmarks. Results show that the ratio of the number of probe needles available for test access to the number of prebond scan chains determines which prebond scan configuration results in the shortest test time. Maximum prebond scan-in and scan-out shift-clock speeds are determined for dies in a benchmark 3-D design as a function of driver strength and transmission gate width. These clock speeds show that prebond scan test can be performed at a speed that is comparable with scan testing of packaged dies. The maximum clock speed can also be tuned by changing the drive strength of the probe and on-die drivers of the TSV network. Estimates are also provided for peak and average power consumption during prebond scan test for both a high-power pattern per scan chain and an average power pattern per scan chain. On-die area overhead for the proposed method is estimated to be between 1.0% and 2.9% per die for two 3-D benchmarks.

Pre-bond known-good-die (KGD) test is necessary to ensure stack yield for the future adoption of 3-D integrated circuits. Die wrappers that contain boundary registers at the interface between dies have been proposed as a solution for KGD test. It has been shown in the literature that if gated scan flops (GSFs) are substituted for traditional scan flops in the boundary register, then both pre-bond through-silicon-via (TSV) and pre-bond scan test can be performed. The drawback of die wrappers is that two clocked stages are added to each path that crosses a die boundary. In this paper, a bypass mode is added to GSFs to avoid the extra clock stages and retiming is used to recover the additional delay added to TSV paths by design-for-test insertion. Retiming is performed at both die and stack level, and a logic redistribution is proposed to improve the results of die-level retiming. The proposed methods are evaluated through simulations using two logic-on-logic 3-D benchmarks and one modular processor partitioned between two dies. Results show that in most cases, retiming at both the die-level and stack-level is sufficient for recovering the delay added by wrapper boundary cells in cores where all logic and dies are unfixed. Stuck-at ATPG is performed to demonstrate that wrapper insertion and retiming have little impact on pattern count. The area overhead due to wrapper insertion is shown to increase as a circuit is partitioned across an increasing number of stack layers, but the area overhead can be reduced using retiming.

Pre-bond known-good-die (KGD) test is necessary to ensure stack yield for the future adoption of 3D ICs. Die wrappers that contain boundary registers at the interface between dies have been proposed as a solution for known-good-die (KGD) test. It has been shown in the literature that if gated scan flops (GSFs) are substituted for traditional scan flops in the boundary register, then both pre-bond TSV and pre-bond scan test can be performed. The drawback of die wrappers is that two clocked stages are added to each path that crosses a die boundary. In this paper, a bypass mode is added to GSFs to avoid the extra clock stages and retiming is used to recover the additional delay added to through-silicon-via (TSV) paths by design-for-test (DfT) insertion. The proposed method is evaluated through simulations using a logic-on-logic 3D benchmark. Results show that in most cases, retiming at both the die-level and stack-level is sufficient for recovering the delay added by wrapper boundary cells. Stuck-at ATPG is performed to demonstrate that wrapper insertion and retiming have little impact on pattern count. The area overhead due to wrapper insertion is shown to increase as a circuit is partitioned across an increasing number of stack layers, but the area overhead can be reduced using retiming.

Through-silicon via (TSV)-based 3-D stacked ICs are becoming increasingly important in the semiconductor industry, yet pre-bond testing of TSVs continues to be difficult with current technologies. In this paper, we present a test and discrete Fourier transform method for pre-bond testing of TSVs using probe technology. We describe the on-die test architecture and probe technique needed for TSV testing, in which individual probe needles make contact with multiple TSVs at a time. We also describe methods for capacitance and resistance measurements, as well as stuck-at and leakage tests. Simulation results using HSPICE are presented for a TSV network. We demonstrate that we can achieve high resolution in these measurements, and therefore high accuracy in defect detection when we target one or multiple TSVs at a time. We also show that the test outcome is reliable even in the presence of process variations or multiple defective TSVs.

Pre-bond testing of TSVs and die logic is a significant challenge and a potential roadblock for 3D integration. BIST solutions introduce considerable die area overhead. Oversized probe pads on TSVs to provide pre-bond test access limit both test bandwidth and TSV density. This paper presents a solution to these problems, allowing a probe card to contact TSVs without the need for probe pads, enabling both TSV and pre-bond scan test. Two possible pre-bond scan test configurations are shown - they provide varying degrees of test parallelism. HSPICE simulations are performed on a logic-on-logic 3D benchmark. Results show that the ratio of the number of probe needles available for test access to the number of pre-bond scan chains determines which pre-bond scan configuration results in the shortest test time. Maximum pre-bond scan-in and scan-out shift-clock speeds are determined for dies in a benchmark 3D design. These clock speeds show that pre-bond scan test can be performed quickly, at a speed that is comparable to scan testing of packaged dies. The maximum clock speed can also be tuned by changing the drive strength of the probe and on-die drivers of the TSV network. Estimates are also provided for peak and average power consumption during pre-bond scan test. On-die area overhead for the proposed method is estimated to be between 1.0% and 2.2% for three dies in the 3D stack.

Pre-bond testing of TSVs has been identified as a major challenge for yield assurance in 3D ICs. We present a defective-TSV localization technique based on pre-bond probing of a network of TSVs. We describe an efficient algorithm for designing parallel TSV test sessions such that test time is reduced and a given number of faulty TSVs within the TSV network can be uniquely identified. Optimization results for various networks of TSVs highlight significant reduction in test time using the proposed method.

Technology scaling for higher performance and lower power consumption is being hampered today by the bottleneck of interconnect lengths. 3D integrated circuits (3DICs) based on through-silicon vias (TSVs) have emerged as a promising solution for overcoming the interconnect bottleneck. However, testing of 3D ICs remains a significant challenge, and breakthroughs in test technology are needed to make 3Dintegration commercially viable. This paper presents a survey of test challenges for 3D ICs and describes recent innovations on various aspects of 3D testing and DfT. Topics covered include pre-bond testing (BIST and TSV probing), optimizations for post bond testing, and cost modeling for 3D integration and associated test flows.

Through-Silicon Via (TSV)-based 3D stacked ICs (SICs) are becoming increasingly important in the semiconductor industry, yet pre-bond testing of TSVs continues to be difficult with current technologies. In this paper, we present a test and DFT method for pre-bond testing of TSVs using probe technology. We describe the on-die test architecture and probe technique needed for TSV testing, in which individual probe needles make contact with multiple TSVs at a time. We also describe methods for capacitance and resistance measurements, as well as stuck-at and leakage tests. Simulation results using HSPICE are presented for a TSV network. We demonstrate that we can achieve high resolution in these measurements, and therefore high accuracy in defect detection when we target one or multiple TSVs at a time. We also show that the test outcome is reliable even in the presence of process variations or multiple defective TSVs.

Through-silicon via (TSV)-based 3-D stacked ICs (SICs) are becoming increasingly important in the semiconductor industry. In this paper, we address test architecture optimization for 3-D stacked ICs implemented using TSVs. We consider two cases, namely 3-D SICs with die-level test architectures that are either fixed or still need to be designed. We next present mathematical programming techniques to derive optimal solutions for the architecture optimization problem for both cases. Experimental results for three handcrafted 3-D SICs comprising of various systems-on-a-chip (SoCs) from the ITC'02 SoC test benchmarks show that compared to the baseline method of sequentially testing all dies, the proposed solutions can achieve significant reduction in test length. This is achieved through optimal test schedules enabled by the test architecture. We also show that increasing the number of test pins typically provides a greater reduction in test length compared to an increase in the number of test TSVs. Furthermore, we show that shorter test lengths are generally achieved with the larger, more complex dies lower in the stack. This is because test data must pass through every die lower in a stack in order to reach its target die, and with the larger dies lower in the stack, more test bandwidth may be provided to these dies using fewer routing resources.

Testing of 3D stacked ICs (SICs) is becoming increasingly important in the semiconductor industry. In this paper, we address the problem of test architecture optimization for 3D stacked ICs implemented using Through-Silicon Vias (TSVs) technology. We consider 3D-SICs with both fixed given and yet-to-be-designed test architectures on each die and show that both corresponding problem variants are NP-hard. We next present mathematical programming techniques to derive optimal solutions for these problems. Experimental results for three handcrafted 3D-SICs of various SOCs from the ITC'02 SOC test benchmarks show that compared to the baseline method of sequentially testing all dies in a stack, the proposed solutions can achieve up to a 57% reduction in test time. We also show that increasing the number of test pins provides a greater reduction in test time compared to an increase in the number of TSVs. Furthermore, it is shown that 3D stacks with large and complex dies at lower layers require less test time than stacks with complex dies at higher layers.

Testing of three-dimensional (3D) stacked ICs (SICs) is starting to receive considerable attention in the semiconductor industry. Since the die-stacking steps of thinning, alignment, and bonding can introduce defects, there is a need to test multiple subsequent partial stacks during 3D assembly. We address the problem of test-architecture optimization for 3D stacked ICs to minimize overall test time when either the complete stack only, or the complete stack and multiple partial stacks, need to be tested. We show that optimal test-architecture solutions and test schedules for multiple test insertions are different from their counterparts for a single final stack test. In addition, we present optimization techniques for the testing of TSVs and die-external logic in combination with the dies in the stack.

System-on-chip (SOC) designs comprised of a number of embedded cores are widespread in today's integrated circuits. Embedded core-based design is likely to be equally popular for three-dimensional integrated circuits (3D ICs), the manufacture of which has become feasible in recent years. 3D integration offers a number of advantages over traditional two-dimensional (2D) technologies, such as the reduction in the average interconnect length, higher performance, lower interconnect power consumption, and smaller IC footprint. Despite recent advances in 3D fabrication and design methods, no attempt has been made thus far to design a 1500-style test wrapper for an embedded core that spans multiple layers in a 3D SOC. This paper addresses wrapper optimization in 3D ICs based on through-silicon vias (TSVs) for vertical interconnects. Our objective is to minimize the scan-test time for a core under constraints on the total number of TSVs available for testing. We present two polynomial-time heuristic solutions. Simulation results are presented for embedded cores from the ITC 2002 SOC test benchmarks.