As SRAM-based caches are hitting a scaling wall, manufacturers are integrating DRAM-based caches into system designs to continue increasing cache sizes. While DRAM caches can improve the performance of memory systems, existing DRAM cache designs suffer from high miss penalties, wasted data movement, and interference between misses and demands. In this paper, we propose TDRAM, a novel DRAM microarchitecture tailored for caching. TDRAM enhances existing DRAM, such as HBM3, by adding small, low-latency mats to store tags and metadata on the same die as the data mats. These mats enable tag and data access in lockstep, in-DRAM tag comparison, and conditional data response based on the comparison result (reducing wasted data transfers), akin to SRAM cache mechanisms. TDRAM further optimizes hit and miss latencies through opportunistic early tag probing. Moreover, TDRAM introduces a flush buffer to store conflicting dirty data on write misses, eliminating data bus turnaround delays on write demands. We evaluate TDRAM in a full-system simulation using a set of HPC workloads with large memory footprints, showing that TDRAM, on average, provides $2.65 \times$ faster tag checks, $1.23 \times$ speedup, and 21% less energy consumption compared to state-of-the-art commercial and research designs.

In computational sensing and imaging, optics can perform some of the processing tasks traditionally performed by digital signal processing and, conversely, digital signal processing can perform some of the processing tasks traditionally performed by optics. This approach thus provides a new framework for reducing electrical power dissipated by sensors: for a criterion end-to-end functional performance, design the optics such that the digital computation cost is as low as possible. There are two such strategies to designing optics to reduce electrical power dissipation: creating optics that produce an optical signal that either 1) requires less digital processing for the criterion functional performance or 2) requires fewer pixels and hence less read, A/D conversion, and signal transfer power. A special-purpose diffractive optical element integrated with a CMOS image sensor photodetector array with simple on-chip processing reveal power reduction in one operational mode roughly two orders of magnitude compared to that in a functionally equivalent traditional lens-based sensors.

Images captured under low-light conditions are noisy as a result of photon statistics and quantization error, among other reasons. Such statistical limitations can be reduced by using pixels with larger areas, but this approach leads to aliasing artifacts. We propose a maximum-likelihood version of super-resolution for low-light conditions in which Fourier image coefficients and unknown spatial shifts between captured frames are estimated iteratively, all in order to produce the single image with high expected fidelity. We illustrate the power of our method on both one-dimensional synthetic data and on two-dimensional medical images.

Energy consumption has become a major constraint on the capabilities of computer systems. In large systems the energy consumed by Dynamic Random Access Memories (DRAM) is a significant part of the total energy consumption. It is possible to calculate the energy consumption of currently available DRAMs from their datasheets, but datasheets don't allow extrapolation to future DRAM technologies and don't show how other changes like increasing bandwidth requirements change DRAM energy consumption. This paper first presents a flexible DRAM power model which uses a description of DRAM architecture, technology and operation to calculate power usage and verifies it against datasheet values. Then the model is used together with assumptions about the DRAM roadmap to extrapolate DRAM energy consumption to future DRAM generations. Using this model we evaluate some of the proposed DRAM power reduction schemes.