Global routing is a critical stage in electronic design automation (EDA) that enables early estimation and optimization of the routability of modern integrated circuits with respect to congestion, power dissipation, and design complexity. Batching is a primary concern in top-performing global routers, grouping nets into manageable sets to enable parallel processing and efficient resource usage. This process improves memory usage, scalable parallelization on modern hardware, and routing congestion by controlling net interactions within each batch. However, conventional batching methods typically depend on heuristics that are computationally expensive and can lead to suboptimal results (oversized batches with conflicting nets, excessive batch counts degrading parallelization, and longer batch generation times), ultimately limiting scalability and efficiency. To address these limitations, a novel batching algorithm enhanced with Wasserstein generative adversarial networks (WGANs) is introduced in this paper, enabling more effective parallelization by generating fewer higher-quality batches in less time. The proposed algorithm is tested on the latest ISPD’24 contest benchmarks, demonstrating up to 40% runtime reduction with only 0.002% degradation in routing quality as compared to state-of-the-art router.

Industrial Systems-on-Chips (SoCs) often comprise hundreds of thousands to millions of nets and millions to tens of millions of connectivity edges, making empirical evaluation of hardware–Trojan (HT) detectors on realistic designs both necessary and difficult. Public benchmarks remain significantly smaller and hand-crafted, while releasing truly malicious RTL raises ethical and operational risks. This work presents an automated and scalable methodology for generating HT-like patterns in industry-scale netlists whose purpose is to stress-test detection tools without altering user-visible functionality. The pipeline (i) parses large gate-level designs into connectivity graphs, (ii) explores rare regions using SCOAP testability metrics, and (iii) applies parameterized, function-preserving graph transformations to synthesize trigger–payload pairs that mimic the statistical footprint of stealthy HTs. When evaluated on the benchmarks generated in this work, representative state-of-the-art graph-learning models fail to detect Trojans. The framework closes the evaluation gap between academic circuits and modern SoCs by providing reproducible challenge instances that advance security research without sharing step-by-step attack instructions.

Online training is central for increasing the speed and accuracy of edge ML. In this paper, a novel framework is presented to execute training and inference operations on-chip using analog memory. With the proposed system, no data communication between memory and the processor is needed. In addition, the framework is designed in fully analog domain, eliminating the need for using expensive analog-to-digital and digital-to-analog converters. Finally, the same circuit is utilized for both pairwise training and inference. To evaluate the performance within the computational constraints of Cadence, a reduced ten-class MNIST dataset is generated by down-sampling the MNIST digit images from 784 features to 16 features. A total of 45 systems are trained to perform the individual pairwise classifications of MNIST data. The proposed system exhibits an average accuracy of 91.14% exceeding the performance of a digital 6-bit resolution system. The proposed framework is designed and demonstrated in Cadence Virtuoso with TSMC 65 nm technology node. The pairwise training and inference circuit occupies an area of 0.243 mm2and consumes 6.593 fJ energy per each multiply-accumulate (MAC) operation.

Hardware Trojans (HTs) can be maliciously inserted in integrated circuits (ICs) during various phases of the circuit design process, posing significant security risks. Existing solutions are limited by their dependency on golden references, poor scalability, and suffer from high false positive and negative rates, making them less effective in detecting and mitigating HTs. In this paper, a NetVGE framework is proposed for efficient HT detection at the register-transfer (RT) level. NetVGE generates weighted variable dependency graphs, which are embedded in a latent space in an unsupervised manner using the knowledge graph embedding (KGE) algorithm. The embedded HTs are accurately detected in the latent space with a HittER model. The effectiveness of NetVGE is demonstrated based on RT-level Trust-HUB benchmarks, yielding high recall (93%) and precision (98%). These results validate NetVGEs effectiveness for realworld hardware cybersecurity applications and demonstrate its scalability with increasing IC size compared to state-of-the-art HT detection methods.

Through silicon vias (TSVs) play a critical role in three-dimensional (3-D) packaging, facilitating the development of smaller, faster, and more efficient electronic devices crucial across various industries, such as telecommunications and computing. With existing package-level computer-aided design (CAD) tools, simulation of a TSV array is computationally prohibitive due to the underlying field solver methods. Moreover, the existing TSV analytical models primarily address capacitive and resistive TSV characteristics, disregarding TSV self- and mutual inductance. Accurate modeling for emerging high-bandwidth applications that benefit from 3-D integration (e.g., a THz light detection and ranging (LiDAR) 3-D integrated sensor with mixed-signal machine learning accelerators), however, necessitate consideration of TSV self-inductance and mutual coupling. To address this challenge, an analytical RLCG model is proposed in this paper for two signal-ground (SG) pairs of TSVs. To validate the proposed analytical model, a physical model of a coupled TSV-based network is designed in ANSYS HFSS 3-D field solver. Consequently, the analytical model is validated against the physical model for a broad range of typical TSV parameters, yielding over 90% for up to 100 GHz. Based on simulation results, the proposed model facilitates precise and rapid analysis of a TSV based network.

Effective delivery of power from PCB to integrated circuits (ICs) is a primary concern in modern integrated systems. Vertical power delivery with embedded on/in-interposer voltage regulators (VRs) is a promising approach for mitigating the PCB-to-die power loss in high performance systems. To enable distributed vertical power delivery systems, conversion and routing losses (which heavily depend on the number and placement of embedded VRs) should be co-optimized with respect to area constraints and impedance characteristics of the redistribution layer (RDL). In this paper, an automated optimization framework for maximizing power efficiency and density in distributed vertical power delivery systems is proposed. The framework comprises analytical power loss models and model-driven methodology for optimizing the size and placement of the VRs as well as efficiency of the individual converters. The framework is demonstrated with a vertical power system comprising of 8 to 96 embedded VRs, delivering a 1-kW power at 2 A/mm2 to a 500 mm2 functional die. The optimized power delivery system exhibits < 20% loss as compared with > 30% loss with a commercial product with similar power load characteristics.

Planar inductors are widely utilized in traditional, PCB-level switching mode power supplies. To mitigate prohibitive power loss in modern high-performance integrated systems, power converters should be embedded closer to points-of-load (POLs). The large footprint and limited inductance density of planar inductors, is a primary concern in these modern power delivery architectures. To mitigate the insufficient inductor current density, vertically stacked on/in-interposer inductors have recently proposed. To facilitate vertically stacked inductors in practical systems, device architecture and respective analytical models are required. In this paper, a fully embedded multi-layer spiral square inductor is proposed to maximize inductance density through coupling. The inductor is designed and simulated with COMSOL Multiphysics, yielding the inductance density of up to 440 nH/mm2 (as compared to 127 nH/mm2 with state-of-the-art). Comprehensive design space exploration of inductor performance is, however, impractical with COMSOL due to high computational complexity of the underlying Finite Element Method (FEM). To facilitate an efficient exploration of tradeoffs with the proposed architecture, analytical physics-aware models are proposed. The model is validated based on COMSOL Multiphysics with up to ten layers, exhibiting over 95.8% accuracy with more than two layers.

Modern high performance integrated systems demand high-power (>1 kW) to be delivered at high current density (>2 A/mm2) from PCB to points-of-load (POLs) on-chip. Efficient delivery of high-quality power from PCB to POLs is a primary concern in modern high-power high-density integrated systems. With traditional power delivery approaches, high voltage is converted to high current on PCB, yielding prohibitively high power loss in horizontal packaging interconnect components. One approach to reduce this loss is with vertical power delivery (VPD), i.e., to deliver low current at high voltage horizontally and convert it to high current low voltage close to POLs. Voltage regulators (VRs) integrated within small footprint near POLs, however, exhibit high switching and inductor losses. As a result, state-of-the-art VPD systems still exhibit high IR voltage drops, power efficiency of less than 70%, and high thermal dissipation. Thus, the design of compact power efficient VRs is a primary concern with VPD approach. To enhance the overall performance of the PCB-to-POL power delivery system, distributed VPD is considered and architecture-specific design of VRs is investigated in this paper. The design methodology for determining optimal number and placement of VRs for a given power delivery architecture is also proposed. The approach has been demonstrated with on-interposer 12V/1V power converters, comprising Gallium Nitride (GaN) power devices and state-ofthe-art inductors and capacitors, yielding 85% power efficiency with 1-kA load at 2 A/mm2.

Hardware Trojans (HTs) are malicious circuits that can be inserted into integrated circuits (ICs) during the design, manufacturing, or packaging phases. HTs can cause a variety of security and safety problems, such as data theft, denial-of-service attacks, and physical damage. A scalable reference-free framework is introduced in this paper for netwise gate-level detection of existing and unknown HTs. The proposed framework consists of embedding-based automated netlist graph analysis and a supervised convolution-based classification of the individual IC net embeddings. A novel convolution algorithm for learning embedded IC graphs has been developed to overcome fundamental scalability limitation of existing graph convolutional neural networks. The performance of the proposed framework is experimentally demonstrated based on the TrustHub TRIT-TC benchmark suite, yielding a high recall of 96% and a precision of 86% for the netwise detection. The individual HT-compromised nets are highlighted within less than 0.1 seconds in >17,000-gate ICs. The proposed framework provides a scalable way to detect existing and unknown HTs without relying on HT-free reference ICs and can be effectively applied to large complex modern ICs. The unique combination of these characteristics makes the proposed framework more practical for real-world hardware cybersecurity applications as compared with prior art.

A multiterminal obstacle-avoiding pathfinding approach is proposed. The approach is inspired by deep image learning. The key idea is based on training a conditional generative adversarial network (cGAN) to interpret a pathfinding task as a graphical bitmap and consequently map a pathfinding task onto a pathfinding solution represented by another bitmap. To enable the proposed cGAN pathfinding, a methodology for generating synthetic dataset is also proposed. The cGAN model is implemented in Python/Keras, trained on synthetically generated data, evaluated on practical VLSI benchmarks, and compared with state-of-the-art. Due to effective parallelization on GPU hardware, the proposed approach yields a state-of-the-art-like wirelength and a better runtime and throughput for moderately complex pathfinding tasks. However, the runtime and throughput with the proposed approach remain constant with an increasing task complexity, promising orders of magnitude improvement over state-of-the-art in complex pathfinding tasks. The cGAN pathfinder can be exploited in numerous high throughput applications, such as, navigation, tracking, and routing in complex VLSI systems. The last is of particular interest to this work.

While financially preferable, pre-silicon hardware Trojan (HT) detection remains a primary security challenge in modern integrated circuits (ICs) In this paper, a pre-silicon framework is developed for identifying rarely triggered nets (including those of HTs) Unsupervised knowledge graph embedding is utilized to transform the conditional triggering probability of IC nets into the Euclidean distance between the nets’ embeddings The proposed approach is not limited by HT types/IC sizes and is reference-free The framework is evaluated with TrustHub benchmarks, fully supporting the theoretical results HTs are identified in the center of the embeddings’ cloud, reducing the HT search space by over 10X.

A machine learning (ML) design framework is proposed for adaptively adjusting clock frequency based on propagation delay of individual instructions. A random forest model is trained to classify propagation delays in real time, utilizing current operation type, current operands, and computation history as ML features. The trained model is implemented in Verilog as an additional pipeline stage within TigerMIPS processor. The modified system is experimentally tested at the gate level in 45 nm CMOS technology, exhibiting simultaneously a speedup of 70 percent and an energy reduction of 30 percent with coarse-grained ML classification as compared with the baseline TigerMIPS. A speedup of 89 percent is demonstrated with finer granularities with a simultaneous 15.5 percent reduction in energy consumption.

The ubiquitous applications of the Internet of Things (IoT) devices and the increasing computational capabilities of neural networks (NNs) have led to a new era of edge computing and a paradigm known as edge intelligence (EI). With EI, the goal is to maximize the utilization of resources available within an edge device, offloading only the most compute-intensive operations to the cloud. In this article, we propose to leverage the close similarity between the internal architecture of a typical network decoder and an NN for deep learning on decoders. The proposed NN-over-decoder is developed in Verilog and synthesized on field-programmable gate array (FPGA). Based on experimental results, the system exhibits power consumption of the same order of magnitude as a baseline decoder and negligible memory overhead while increasing local hardware utilization, alleviating the high communication load in typical communication devices, and offering scalable multiply–accumulate (MAC)/cycle performance compared with the state of the art.

Obstacle-avoiding multiterminal net routing approach is proposed. The approach is inspired by deep learning image processing. The key idea is based on training a conditional generative adversarial network (cGAN) to interpret a routing task as a graphical bitmap and consequently map it to an optimal routing solution represented by another bitmap. The system is implemented in Python/Keras, trained on synthetically generated data, evaluated on typical high-resolution benchmarks, and compared with state-of-the-art traditional deterministic and deep learning solutions. The proposed system yields between 10.75x and 83.33x speedup over the traditional router without wirelength overhead due to effective parallelization on GPU hardware.

A global router is proposed that learns from routed circuits and autonomously routes unseen layouts. The uniqueness of this approach is in redefining the global routing as a classical image-to-image processing problem. The imaging problem is efficiently solved with a deep learning system, comprising a variational autoencoder and custom loss function. This fundamentally new routing method provides a natural way for global routing parallelization. The deep router is designed, trained, and tested on an unseen 64×64 ISPD'98 benchmark circuit. The test results yield 3.2% decrease in routability and over 5X speedup in runtime as compared with the state-of-the-art FastRoute router.

Mixed-signal machine learning (ML) classification has recently been demonstrated as an efficient alternative for classification with power expensive digital MOSFET circuits. In this paper, a topology based on independent double-gate (IDG) FinFET devices is proposed for classifying high-dimensional input data into multi-class output space with less power and area as compared with state-of-the-art MOSFET classifiers. To facilitate a high-resolution multiplication as a part of the classifier predictions, ML features and feature weights are, respectively, fed to the back and front gate inputs of the individual IDG-FinFET transistors. A classifier that considers the decisions of the individual predictors is designed at 30 nm FinFET technology node and operates at 333 MHZ with nominal supply voltage of one volt. To evaluate the performance of the classifier, a reduced MNIST dataset is generated. The original resolution is reduced from 28×28 features to 9×9 features and the most important features are selected with sequential backward selection algorithm. The system is simulated in SPICE, exhibiting prediction accuracy of 90%, energy consumption of 25 pJ per classification (over four times lower than similar state-of-the-art classifiers), area of 1,365 μm2, and a stable response under a wide range of system variations.

Reliably and power efficiently securing integrated systems against advanced power analysis attacks (PAAs) is a significant design challenge in modern integrated circuits. Power masking and hiding are typical countermeasures for increasing system resilience for power attacks at the expense of the overall system performance and power efficiency. These method are, however, not able to alert the user or trigger additional protective actions in case of the attack. In this paper, a method for detecting power attacks in real-time is proposed. The proposed approach exploits statistical methods to analyze the on-chip voltage variations across an on-chip power grid and detect the attacker probe connected to the system. The problem of the full security coverage of the power grid is formulated and solved in this paper. Adjusting the density of the on-chip sensors and exploiting sparse analysis techniques is considered to simultaneously enhance the accuracy and power efficiency of the proposed solution. The proposed attack detection system is designed, simulated, and evaluated in Simulink based on IBM microprocessor benchmark data. Machine learning (ML) models are trained in Python and with scikit-learn ML library. The proposed system has been demonstrated to efficiently detect PAA within a period of time that is orders of magnitude shorter than a typical attack duration length. The system is expected to exhibit high detection accuracy and power efficiency across a wide spectrum of integrated systems.

To support the demand for energy autonomy, many of the future IoT edge devices will be powered from non-conventional, energy harvesting and wireless power sources. While convenient, sustainable, and robust, wireless power transfer (WPT) exhibits limited efficiency compared with the traditional wired power approaches, presenting a primary design challenge for practical IoT systems. Non-radiative mid-range WPT from a single power source to several power loads and from several power sources to a single power load has recently been experimentally demonstrated. Alternatively, WPT among multiple, simultaneously transmitting and receiving devices is a primary concern in future IoT systems with numerous interconnected heterogeneous objects. Furthermore, the dynamic nature of certain distributed IoT systems has a significant effect on WPT interactions among the numerous, mobile in space power devices. WPT that exploits the lossless characteristics of strong-coupled resonant regime is explored in this work as a method for efficiently transferring power among multiple, dynamically connected and disconnected IoT end devices. The efficiency of the power transfer is investigated in dense and sparse IoT systems in terms of the number of IoT devices located within limited space. Based on the results of this work, interactions among wirelessly powered devices have significant effect on the power transfer. Efficiency of power transfer increases with increasing transmitter-receiver coupling. Alternatively, densely clustered power transmitters or receivers may degrade the system-wide power transfer and efficiency. Intuition behind systematically optimized utilization of the WPT-based energy budget in future IoT systems is also provided.

Abstract-Efficiently and reliably managing high quality power is a primary challenge in Internet of Things (IoT) systems. Based on current projections, future IoT will provide vast interconnectedness of embedded devices and sensors, many of which will be powered up wirelessly from spatially distributed power supplies or locally from energy harvesting sources. The energy budget, constrained by inherently lower quality of power of these non-traditional power sources, will become a critical system resource and a primary limiting factor for scalability of future IoT systems. Distributed on-chip power regulation is necessary for efficiently delivering high quality power to high performance heterogeneous integrated circuits (ICs). A multi- feedback system with distributed on-chip power supplies deliver- ing current to billions of non-linear circuits is characterized by complex interactions among the heterogeneous power supplies and loads. These modern multi-feedback systems exhibit high design complexity and degraded stability. No straightforward method exists to efficiently design a stable multi-feedback power delivery system. An automated design and analysis flow for stable, high quality power delivery is proposed in this work based on the passivity of heterogeneous integrated systems. The algorithm is evaluated based on ISPD benchmark circuits and shows that the generated power delivery system addresses both the quality of power (QoP) and stability requirements. A distributed power delivery system is designed based on the passivity criterion and fabricated in 28 nm CMOS technology. The system is tested under a wide range of load, voltage, and temperature variations that are typical for modern heterogeneous ICs. The system exhibits high performance and stable response.

High quality power delivery for on-chip high performance integrated circuits is a significant design challenge in modern functionally diverse systems with multiple power domains. To provide a high quality power delivery system with dynamically changing voltages and transient currents, the onchip power needs to be regulated in real time, within each power domain. To exploit the advantages of existing switching and linear power supplies, a heterogeneous power delivery system has recently been proposed based on the principle of separation of power conversion and regulation, lowering the overall energy loss while requiring small on-chip area. The power efficiency of the system is shown to be a strong function of the clustering of the power supplies - the specific configuration in which power converters and regulators are co-designed. A recursive clustering algorithm with polynomial computational complexity is proposed for an optimal real time power distribution system with minimum power losses. The proposed algorithm is evaluated on IBM power grid benchmark circuits and two multi-power domain circuits, yielding up to a 21% increase in power efficiency, and orders of magnitude speedup in runtime with the proposed recursive clustering algorithm.

A digitally controlled current starved pulse width modulator (PWM) is described in this paper. The current from the power grid to the ring oscillator is controlled by a header circuit. By changing the header current, the pulse width of the switching signal generated at the output of the ring oscillator is dynamically controlled, permitting the duty cycle to vary between 25% and 90%. A duty cycle to voltage converter is used to ensure the accuracy of the system under process, voltage, and temperature (PVT) variations. A ring oscillator with two header circuits is proposed to control both duty cycle and frequency of the operation. Analytic closed-form expressions for the operation of a PWM are provided. The accuracy and performance of the proposed PWM is evaluated with 22-nm CMOS predictive technology models under PVT variations. An error of less than 3.1% and 4.4% in the duty cycle, respectively, with and without constant frequency control is reported for the PWM. A constant operation frequency with less than 1.25% period variation is demonstrated. The proposed PWM is appropriate for dynamic voltage scaling systems due to the small on-chip area and high accuracy under PVT variations.

A digitally controlled current starved pulse width modulator is described in this paper. The current from the power grid to the ring oscillator is controlled by a header circuit. By changing the header current, the pulse width of the switching signal generated at the output of the ring oscillator is dynamically controlled, permitting the duty cycle to vary between 50% and 90%. A duty cycle to voltage converter is used to ensure the accuracy of the system under process, voltage, and temperature (PVT) variations. The accuracy and performance of the proposed digitally controlled pulse width modulator is evaluated with 22 nm CMOS predictive technology models under PVT variations. The proposed pulse width modulator is appropriate for dynamic voltage scaling systems due to the small on-chip area and high accuracy under process, voltage, and temperature variations. Although the frequency of the switching signal is affected by changes in the duty cycle, the frequency variations are typically negligible.

Clock distribution networks are an essential element of a synchronous digital circuit, a significant power consumer and highly sensitive to process, voltage, and temperature variations. Mesh- and crosslink-based topologies reliably compensate for skew variations in these networks, albeit with a significant increase in dissipated power as compared to variation-sensitive low power clock trees. Existing crosslink-based methods, however, only address skew from an algorithmic perspective at the network topology level. Guidelines for inserting crosslinks within a buffered low power clock tree are provided in this paper. Physical constraints, such as the size of the crosslink and exact location between the driving and load buffers, are analytically described. Metrics to determine the most energy efficient non-tree topology are provided based on closed-form expressions, and verified with simulation.

Clock distribution networks are an important design issue that is highly dependent on delay variations and load imbalances, while requiring power efficiency. Existing mesh solutions significantly increase the dissipated power, whereas existing link based methods only address skew caused by variations and do not consider power consumption. The power dissipated by the inserted crosslinks within a buffered clock tree is investigated in this paper, and is shown to be a strong function of the resistance and capacitance of the crosslink. A crosslink may be power efficient despite the presence of short-circuit currents caused by multiple drivers in a non-tree clock network. The power characteristics of crosslink size and placement are also discussed, showing that the crosslink is best placed as close as possible to the target leaves of the tree. Crosslink insertion as both an alternative and complement to buffer sizing for low power skew reduction is also considered.