This paper presents an enhanced floating-point multiply-add (FMA) design for the Intel E-Core processor. FMA is one of the most widely used operation in many applications. The proposed FMA is executed in 4 cycles, fully pipelined, handles SSE/AVX operations for scalar/packed IEEE single and double precision, and supports all four rounding modes. Also, the proposed FMA fully supports both denormal inputs and underflow outputs without microcode assistance. To achieve the 4-cycle FMA with full denormal support, several optimization techniques are applied: one-way alignment, radix-16 Booth encoding for the multiplier, merged J-bit correction and aligned significand with the multiply array, modified leading zero anticipation (LZA) for masking the underflow, parallel sticky and all-ones detection with the normalization, and merged two’s complement with the rounding logic. As a result, the proposed FMA achieved not only full denormal support but also about 10 – 30% reduced area and about 10 – 20% reduced latency compared to the traditional FMAs.

This paper presents an enhanced floating-point adder (FADD) design for the Intel E-Core processor. Floating-point addition and subtraction are two of the most widely used operations in many applications. The proposed FADD is executed in 2 cycles, fully pipelined, handles SSE/AVX operations for scalar/packed IEEE single and double precision, and supports all four rounding modes. Also, the proposed FADD fully supports both denormal inputs and underflow outputs without microcode assistance. To achieve the 2-cycle FADD with full denormal support, several optimization techniques are applied: split path algorithm, early alignment and sticky logic, parallel addition, rounding and all-ones detection, and modified leading zero anticipation (LZA) for masking the underflow. As a result, the proposed FADD achieved not only full denormal support but also about 12.5% reduced latency compared to the traditional FADD designs.

The Motorola 68040 floating point unit (FPU) combines three independent state machines, two data paths, and over 100000 transistors to achieve 8-Mflops peak performance and over 3-Mflops Linpack double-precision performance at the introductory speed of 25 MHz. It is optimized for minimum latency and maximum pipelined performance on frequently used double-precision floating point instructions. The FPU is architecturally divided into three piped stages, the conversion unit (CU), the execution unit (XU), and the normalization unit (NU). The control logic is tested using scan to achieve very high ATPG fault coverage while the data paths are tested using functional patterns.>