Static learning is a learning algorithm for retrieving implicit logical relationships between nodes in a netlist. The learning results play an important role in improving automatic test pattern generation (ATPG), such as increasing fault coverage and reducing pattern count. In this work, we study accelerating static learning on graphics processing units (GPUs). By tailoring to the architectural features of GPUs, an algorithm of concurrent static learning is proposed. Multiple learning jobs are carried out simultaneously or concurrently in the same netlist. Moreover, the forward and backward implications of these concurrent jobs are processed as a whole, which leads to better utilization of the computing resources on GPUs. Experiments show that the algorithm can achieve up to 253x speedup against a single-threaded commercial tool and is about 1.8 times better than existing GPU-based solutions.

Due to the continuous advancement of semicon-ductor technologies, there are more defects than ever widely distributed in manufactured chips. In order to meet the high product quality and low defective-parts-per-million (DPPM) goals, Boolean Satisfiability (SAT) technique has been shown to be a robust alternative to conventional APTG techniques, especially for hard-to-detect faults. However, the SAT-based ATPG still confronts two challenges. The first one is to reduce extra computational overhead of SAT modeling, i.e. to transform a circuit testing problem to a Conjunctive Normal Form (CNF) which is the foundation of modern SAT solvers. The second one lies in the SAT solver's efficiency which is brought by the loss of structural information during CNF transformation. In this work, we propose a new SAT-based ATPG approach to address the two challenges mentioned above: (1) To reduce CNF transformation overhead, we utilize a simulation-driven pre-processing for narrowing down the fault propagation and activation logic cones, leading to an improvement in CNF transformation and reduction in runtime. (2) To further improve the solving efficiency, We propose new ranking-based heuristics to build more effective conflict database, enabling the direct solving for small scale instance and a looking-head method for large scale ones. Extensive experimental results on industrial circuits demonstrate that on average the proposed approach could cover 89.67% of the faults failed by a commercial ATPG tool with a comparable runtime.

Applying deep learning (DL) techniques in the electronic design automation (EDA) field has become a trending topic. Most solutions apply well-developed DL models to solve specific EDA problems. While demonstrating promising results, they require careful model tuning for every problem. The fundamental question on "How to obtain a general and effective neural representation of circuits?" has not been answered yet. In this work, we take the first step towards solving this problem. We propose DeepGate, a novel representation learning solution that effectively embeds both logic function and structural information of a circuit as vectors on each gate. Specifically, we propose transforming circuits into unified and-inverter graph format for learning and using signal probabilities as the supervision task in DeepGate. We then introduce a novel graph neural network that uses strong inductive biases in practical circuits as learning priors for signal probability prediction. Our experimental results show the efficacy and generalization capability of DeepGate.

Continued advances in process technology have led to a relentless increase in the design complexity of integrated circuits (ICs). In order to meet the increasing demand of low defective-parts-per-million (DPPM) and high product quality of the complex circuit designs, Boolean Satisfactory (SAT) has worked as a robust alternative to conventional APTG techniques. In SAT-based ATPG, logic cones related to the target faults are transformed to Boolean formulas, and standard SAT solving procedures are then used for solving these formulas. Recently, artificial intelligence (AI) techniques have shown great potential in speeding-up SAT solvers. However, the high diversity of the structural characteristics within the logic cones of target faults limits the AI techniques being used for SAT-based ATPG. To meet this challenge, this paper proposes a neural fault analysis technology that is made up of a multi-stage learning model and the testability classifier to highly increase the SAT-based ATPG solving efficiency. The multi-stage learning model is composed of a generative model with a topology structure discriminator and a conflict structure discriminator. It is trained for high-quality data synthesis. Then the testability classifier is trained for adaptive heuristic selection and effective initialization in SAT-based ATPG. Experimental results on both open-source and industrial circuits demonstrate that the neural fault analysis can reduce the SAT solving time by 34.79% and reduce the runtime of SAT-based ATPG by 7.43% on average. It is also shown that the proposed neural fault analysis can cover 9.14% of the faults failed by the conventional SAT-based ATPG framework with a comparable runtime.

Test point insertion (TPI) is a widely used technique for testability enhancement, especially for logic built-in self-test (LBIST) due to its relatively low fault coverage. In this paper, we propose a novel TPI approach based on deep reinforcement learning (DRL), named DeepTpi. Unlike previous learning-based solutions that formulate the TPI task as a supervised-learning problem, we train a novel DRL agent, instantiated as the combination of a graph neural network (GNN) and a Deep Q-Learning network (DQN), to maximize the test coverage improvement. Specifically, we model circuits as directed graphs and design a graph-based value network to estimate the action values for inserting different test points. The policy of the DRL agent is defined as selecting the action with the maximum value. Moreover, we apply the general node embeddings from a pretrained model to enhance node features, and propose a dedicated testability-aware attention mechanism for the value network. Experimental results on circuits with various scales show that DeepTPI significantly improves test coverage compared to the commercial DFT tool. The code of this work is available at https://github.com/cure-lab/DeepTPI.

The remarkable growth of the circuit size and complexity is primarily due to the advances of VLSI design and manufacturing technologies. The on-chip linear sequential test compression has become the de facto industrial mainstream DFT methodology in reducing the overall cost of testing large chips. In this paper, we propose a novel and efficient compression-aware ATPG method to significantly boost the performance of ATPG and reduce pattern count. The proposed approach first analyzes the intrinsic dependency of the equations determined by a linear sequential decompressor to build Maximal Linear Independent Group (MLIG). Next it computes the implied values given ATPG generated test cubes based on MLIG. The implied values can significantly improve the test compaction and reduce the ATPG run time due to the reduction of value conflicts between ATPG and compression. The proposed approach does not affect test coverage, requires no extra hardware support, and can be applied to any linear sequential compression scheme. Experimental results on several industrial designs demonstrate that on average the proposed approach can reduce the number of ATPG patterns by 7.57% and the ATPG run time by 28.4%.

Timing exceptions are commonly used to indicate that the timing of certain paths have been relaxed so as to enable the design to meet timing closure. Generating scan-based test patterns without considering timing exceptions can lead to invalid test responses, resulting in unpredictable test quality impact. The existing simulation-based solution masks out unreliable signals after a test pattern is generated. If the signals required for detecting the target fault are unreliable and masked out, the generated test pattern fails to detect the target fault, and it is discarded. To achieve an acceptable test coverage, several iterations of test generation with a randomized decision-making process are typically required where different tests are generated for target faults. In this paper, an innovative deterministic ATPG algorithm called TEA (Timing Exception ATPG) is proposed to prevent the generated test patterns from being impacted by timing exceptions. The deterministic algorithm is compatible with the existing simulation-based approach. In this simulation environment, TEA is complete such that for a target fault, the test pattern generated is guaranteed to detect it. If a test pattern cannot be generated using TEA, the target fault is untestable given the timing exception paths in the design and the existing simulation environment. Compared to the existing simulation-based approach, using TEA can generate a more effective test set, improving test coverage, test pattern count, and the total ATPG run time significantly.

As integrated circuit manufacturing advances, the occurrence of systematic defects is expected to be prominent. A methodology for predicting potential systematic defects based on design-for-manufacturability (DFM) guidelines was described earlier. In this paper we first report that, among the faults obtained based on DFM guidelines, there are undetectable faults, and these faults cluster in certain areas of the circuit. Because faults may not perfectly represent potential defect behaviors, defects may be detectable even though the faults that model them are undetectable. Clusters of undetectable faults thus leave areas in the circuit uncovered for potential systematic defects. As the potential defects are systematic, the test escapes can impact the DPPM significantly, and thus lead to circuit malfunction and/or reliability problems after deployment. To address this issue in the context of cell-based design, we propose a logic resynthesis procedure followed by physical design to eliminate large clusters of undetectable faults related to DFM guidelines. The resynthesized circuit maintains design constraints of critical path delay, power consumption and die area. The resynthesis procedure is applied to benchmark circuits and logic blocks of the OpenSPARC T1 microprocessor. Experimental results indicate that both the reduction in the numbers of undetectable faults and the reduction in the sizes of undetectable fault clusters are significant.

Design-for-manufacturability (DFM) guidelines are recommended layout design practices intended to capture layout features that are difficult to manufacture correctly. Avoiding such features prevents the occurrence of potential systematic defects. Layout features that result in DFM guideline violations may not be avoided completely due to the design constraints of chip area, performance, and power consumption. A framework for translating DFM guideline violations into potential systematic defects, and faults, was described earlier. In a cell-based design, the translated faults may be internal or external to cells. In this article, we focus on undetectable faults that are external to cells. Using a resynthesis procedure that makes fine changes to the layout while maintaining the design constraints, we target areas of the design where large numbers of external faults related to DFM guideline violations are undetectable. By eliminating the corresponding DFM guideline violations, we ensure that the circuit does not suffer from low-coverage areas that may result in detectable systematic defects escaping detection, but failing the circuit in the field. The layout resynthesis procedure is applied to benchmark circuits and logic blocks of the OpenSPARC T1 microprocessor. Experimental results indicate that the improvement in the coverage of potential systematic defects is significant.