VLDB 2026 Research / reviewers in the wild / expert
Gokce Sarar
dblp:202/7284
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2024
0000-0001-8526-4061ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › machine learning for EDA
circuit representation learning |
0.8 | 1 | 2024 | Less is More: Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits · DAC 2024 |
Electronic design automation
hardware verification and test |
0.8 | 1 | 2024 | Less is More: Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits · DAC 2024 |
Electronic design automation
machine learning for EDA |
0.8 | 1 | 2024 | Less is More: Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits · DAC 2024 |
Electronic design automation
logic synthesis |
0.2 | 1 | 2024 | Less is More: Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits · DAC 2024 |
Methods — techniques the papers use, named apart from their topics
hop-wise attention · 0.8graph neural network · 0.8gated self-attention · 0.8
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | Less is More: Hop-Wise Graph Attention for Scalable and Generalizable Learning on CircuitsabstractWhile graph neural networks (GNNs) have gained popularity for learning circuit representations in various electronic design automation (EDA) tasks, they face challenges in scalability when applied to large graphs and exhibit limited generalizability to new designs. These limitations make them less practical for addressing large-scale, complex circuit problems. In this work we propose HOGA, a novel attention-based model for learning circuit representations in a scalable and generalizable manner. HOGA first computes hop-wise features per node prior to model training. Subsequently, the hop-wise features are solely used to produce node representations through a gated self-attention module, which adaptively learns important features among different hops without involving the graph topology. As a result, HOGA is adaptive to various structures across different circuits and can be efficiently trained in a distributed manner. To demonstrate the efficacy of HOGA, we consider two representative EDA tasks: quality of results (QoR) prediction and functional reasoning. Our experimental results indicate that (1) HOGA reduces estimation error over conventional GNNs by 46.76% for predicting QoR after logic synthesis; (2) HOGA improves 10.0% reasoning accuracy over GNNs for identifying functional blocks on unseen gate-level netlists after complex technology mapping; (3) The training time for HOGA almost linearly decreases with an increase in computing resources. Source code of HOGA is freely available at: github.com/cornell-zhang/HOGA. Chenhui Deng, Zichao Yue, Cunxi Yu, Gokce Sarar, Ryan Carey, Rajeev Jain, Zhiru Zhang |
DAC | 4 |