For vibration monitoring applications, the wide-bandwidth low noise MEMS accelerometer with high efficiency is required. Conventionally, the sensor resonant frequency is increased to achieve wide bandwidth, which however trades off the sensor sensitivity and degrades system noise and power efficiency (FoM). To meet this challenge, this paper proposed a Microlevers Assisted Hybrid Damping (MAHD) system. Instead of increasing the resonant frequency, the MAHD system employs critical hybrid damping for bandwidth improvement, in order to avoid degradation of the system noise and efficiency. The critical hybrid damping is implemented with an interface circuit providing tunable electrostatic damping force. Asensor structure with microlever is employed to enhance the merit of the critical damping system. The interface circuit is fabricated by a commercial$0.18\mu $m CMOS process and the sensor is fabricated by a commercial surface micromachining process. The measurement results show that, without increasing the sensor resonant frequency, the proposed method improve the system 3dB-bandwidth and 5%-bandwidth by 454% and 550%, respectively. The noise floor is$68.33\mu $g/$\surd $Hz with$600\mu $A current consumption.

For wearable applications, the small size low noise MEMS accelerometer with high efficiency is required. However, the sensitivity of the MEMS sensor reduces with the sensor size scaling down, leading to deterioration of the circuit noise. To meet this challenge, the interface circuit with high-voltage pulse excitation (HVPE) and active noise cancelation readout technique is proposed. The HVPE reduces the circuit noise and the wire resistance noise significantly without introducing additional electrostatic force to the sensor. The drift and mismatch problems of the HVPE are addressed by three specific correction circuits. The power efficiency of the system is optimized by the capacitance-to-voltage converter with active noise cancellation and pulse current supply. The propose HVPE technique is demonstrated in an interface IC fabricated by$0.18\mu $m BCD process and tested with a small size MEMS accelerometer (0.64mm2/axis). The measurement result shows that this IC has achieved a noise floor of$32.5\mu $g/$\surd $Hz with 2kHz bandwidth and$80\mu $W power consumption.

This article reports a high acoustic overload point (AOP) single-ended digital MEMS microphone system. For audio applications in high sound pressure environments, a high AOP MEMS microphone is required. The nonlinearity of MEMS microphone is contributed by the MEMS sensor and the signal path of the readout ASIC. For the MEMS sensor with fixed sensitivity, the low analog supply voltage in the readout ASIC is the main limitation to achieve high AOP. To address this challenge, a single-ended digital MEMS microphone system with a self-adaption loop (SAL) is proposed. The SAL automatically adjusts the gain of the analog front end and the digital back end by detecting the input signal, breaking the limitation of the analog supply voltage on the AOP of the system. Besides, the proposed system features an always-on characteristic, and the power consumption is scalable. A prototype is realized in a$0.153~\mu $m CMOS process, performing 67.34 dB-A SNR with an AOP of 132 dB SPL, consuming$738~\mu $A at 2.4 MHz sampling rate and 1.5-V supply voltage.

This paper presents a$G_{m}$-C integrator-implanted DC servo loop (GMCI2-DSL) and a bulk-driven ripple reduction loop (BD-RRL) for bio-potential readout analog-front-end (AFE) amplifier. The proposed bio-potential readout AFE amplifier employs the GMCI2-DSL and BD-RRL to achieve low noise and significant total harmonic distortion (THD) with small ripple amplitude. A prototype has been taped out using a 0.18-$\mu \text{m}$standard CMOS technology, and the core circuit occupies 880$\mu \text{m}\,\,\times $630$\mu \text{m}$. The mid-band gain is about 40 dB with a 1.3-V supply voltage, and the chip’s quiescent power is 10.8$\mu \text{W}$. The measured results show that the input-referred noise density is 26 nV/$\surd $Hz, and the input-referred integrated noise in the range from 0.5 Hz to 500 Hz is 0.93$\mu V_{rms}$. The measured THD of a 5-$\text{m}V_{pp}$input sinusoidal signal at 5.1 Hz is −64.3 dB without any input offset. The amplitude of residue ripple is achieved as 197.8$\mu \text{V}$around chopping frequency ($f_{ch}$) by ripple suppression. High-fidelity and real-time electrocardiogram (ECG) signals are acquired.

This article presents a single-loop third-order discrete-time delta-sigma modulator (DTDSM) with a 4-bit second-order noise shaping successive approximation register (NS SAR) quantizer. To realize an aggressive noise transfer function (NTF), a novel Finite Impulse Response (FIR) filter is embedded in the NS SAR. As employing a flipped voltage follower (FVF), which offers unity gain instead of an open loop dynamic amplifier, the proposed FIR filter is sharp and insensitive to process, voltage, and temperature (PVT) variation. Fabricated in a 65-nm 1P9M CMOS technology, the prototype DTDSM consumes$44 \mu \text{W}$when operating at a 1.2-V supply voltage and a sampling rate of 2.4 MS/s. It achieves a peak Schreier figure of merit (FoM) of 177.9 dB with a signal-to-noise and distortion-ratio (SNDR) of 91.3 dB at an oversampling ratio (OSR) of 64.

MEMS capacitive accelerometer for the Internet of Things (IoT) applications is designed with open-loop structure rather than close-loop structure to achieve low power consumption. In the open-loop structure, voltage control readout technique is preferred for low cost. However, voltage control readout technique suffers from poor noise performance and low power efficiency (in terms of FoM). In this paper, the weak feedback oversampling successive approximation readout circuit which merges the closed-loop hybrid dynamic amplifier with noise reduction technique is proposed to achieve low noise floor, high power efficiency and high accuracy. The proposed WFB-OSA based readout circuit is fabricated in a commercial$0.18\mu \text{m}$1.8V CMOS process. The measurement result shows that the circuit has achieved a noise floor of$63\mu g/\surd Hz$and an FoM of 14pJ.

MEMS capacitive accelerometer for the Internet of Things (IoT) applications is designed with open-loop structure rather than closed-loop structure to achieve low power consumption. In the open-loop structure, voltage control readout technique is preferred for low cost. However, the voltage control readout technique suffers from low dynamic range and low power efficiency (in terms of$\mathbf {FoM}$). In this paper, the voltage control ratiometric (VCR) readout technique is proposed to improve both dynamic range and power efficiency. The VCR readout technique is demonstrated in a readout circuit fabricated in a commercial 0.18$\mu {\mathrm{ m}}$1.8V/5.0V CMOS process. Compared to the traditional voltage readout circuit fabricated with the same CMOS process and tested with the same sensing element, the VCR readout circuit improves full input signal range by$\mathbf {3.5dB}$(from$\boldsymbol {\pm 8g}$to$\boldsymbol {\pm 12g}$) and the noise floor by$\mathbf {9.5dB}$(from$\mathrm {\mathbf {804~\mu g/}}\sqrt {\mathbf {Hz}} $to$\mathbf {270~\mu g/}\sqrt {\mathbf {Hz}} $). As a result, the dynamic range is improved by$\mathbf {13.0dB}$(from$\mathbf {44.0dB}$to$\mathbf {57.0dB}$), the$\mathbf {Fo}\mathbf {M}_{\mathbf {1}}$is improved from$\mathbf {310pJ}$to$\mathrm {\mathbf {83pJ }}$and the$\mathbf {Fo}\mathbf {M}_{\mathbf {2}}$is improved from$\mathbf {1977~\mu W\cdot \mu g/Hz}$to$\mathbf {796~\mu W\cdot \mu g/Hz}$.