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Awos Kanan

dblp:203/1833 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2017
0000-0002-6817-4870ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Parallel and multicore computing · 33% Hardware accelerators and domain-specific architectures · 33% Electronic design automation · 33%
Databases, data mining, and information retrieval
1 paper
Machine learning and data management · 100%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing
array processor
0.312017
Design Space Exploration of 2-D Processor Array Architectures for Similarity Distance Computation · IEEE Trans. Parallel Distributed Syst. 2017
Electronic design automation
design space exploration
0.312017
Design Space Exploration of 2-D Processor Array Architectures for Similarity Distance Computation · IEEE Trans. Parallel Distributed Syst. 2017
Hardware accelerators and domain-specific architectures
systolic array
0.312017
Design Space Exploration of 2-D Processor Array Architectures for Similarity Distance Computation · IEEE Trans. Parallel Distributed Syst. 2017

Methods — techniques the papers use, named apart from their topics

linear scheduling · 0.63-d computation domain · 0.6
YearPublicationVenuePosition
2017 Design Space Exploration of 2-D Processor Array Architectures for Similarity Distance Computation
abstract
We present a systematic methodology for exploring the design space of similarity distance computation in machine learning algorithms. Previous architectures proposed in the literature have been obtained using ad hoc techniques that do not allow for design space exploration. The size and dimensionality of the input datasets have not been taken into consideration in previous works. This may result in impractical designs that are not amenable for hardware implementation. The methodology presented in this work is used to obtain the 3-D computation domain of the similarity distance computation algorithm. A scheduling function determines whether an algorithm variable is pipelined or broadcast. Four linear scheduling functions are presented, and six possible 2-D processor array architectures are obtained and classified based on the size and dimensionality of the input datasets. The obtained designs are analyzed in terms of speed and area, and compared with previously obtained designs. The proposed designs achieve better time and area complexities.
Awos Kanan, Fayez Gebali, Atef Ibrahim
IEEE Trans. Parallel Distributed Syst.1