In recent years, line-of-sight multiple-input multiple-output (LoS-MIMO) systems have attracted significant attention for their potential in ultra-high throughput space communications. This work addresses E-band LEO satellite transmission with three advances: A dynamic spatio-temporal coupling model for non-orthogonal propagation and non-homologous clocks LoS-MIMO channels. A dual-feedback symbol timing recovery (STR) architecture integrating a frequency-domain timing offset detection (TOD) algorithm that combines an optimized Barton estimator and time-domain resampling, enabling continuous tracking and compensation for thousands of parts-per-million timing frequency deviations (TFDs). Closed-form expressions for TOD estimation error, loop convergence constraints, and residual timing jitter. Simulations under various transmitter delay differences and signal-to-noise ratios verify the resistance to TFD and low residual jitter of the algorithm, showing excellent agreement with theoretical predictions. To our knowledge, this is the first work to address STR architectures across multi-station with non-homologous clocks in satellite-to-ground LoS-MIMO systems, providing a foundational framework for future ultra-high-throughput space communications.

Existing symbol timing recovery (STR) cannot simultaneously meet the performance requirements of broadband satellite internet for throughput, convergence speed, convergence accuracy, and implementation complexity. Focusing on burst single-carrier communications widely used in broadband satellite systems, we proposed a parallel doubly fed STR algorithm combining feedforward and feedback loop, in which the frequency-domain (FD) prefilter is also used to improve the algorithm’s anti-self-noise capability. The corresponding field programmable gate array (FPGA) implementation with low complexity and highly parallel architecture is then accomplished. Simulation results show that the performance degradation caused by the proposed algorithm is less than 0.03 dB compared with the ideal performance when uncoded bit error rate (BER) equals 1e-4 and 64 quadrature amplitude modulation (QAM) modulation is considered. FPGA verification based on the XC7VX690T chip also shows that with 64 parallel inputs and 64-QAM modulation, the throughput rate of information bit can reach 19.2 Gb/s for our design with utilization of 17% look-up tables (LUTs) and 20% digital signal processing (DSP), respectively.