In this article, we propose a flexible and parallelizable hardware architecture of the channel encoding chain for the fifth generation new radio (5G NR) physical downlink control channel (PDCCH). We propose a new polar encoder architecture based on the radix-k processing and fast Fourier transform (FFT) concepts. We also introduce the hardware architectures for cyclic redundancy check (CRC) interleaver and rate matcher for 5G NR PDCCH. We synthesized this complete channel encoding chain on a Virtex Ultrascale+ field-programmable gate-array (FPGA) and show that with the proposed architecture, a codeword throughput of 4.26 Gbps can be realized while consuming as little as 3% of FPGAs resources. The proposed polar encoding architecture can encode from 84 up to 164 resource blocks in the 5G NR frame structure. Encoding of multiple resource blocks can be systematically applied to highly dense (time and frequency) 5G NR fronthaul links supporting multiple antennas.

In this work, a multilevel coding (MLC) based coded modulation scheme with two degrees of freedom in rate flexibility is proposed and compared with a bit-interleaved coded modulation (BICM) scheme from a performance versus complexity perspective. The proposed MLC scheme is based on a rate flexible inner soft-decision polar code and utilizes an outer hard-decision staircase code structure as in the 400ZR concatenated forward error-correcting code. The performance of the MLC scheme is investigated for a range of inner code lengths, inner decoder list sizes, and signaling with 16 and 64 quadrature amplitude modulation, respectively. The MLC is designed such that a portion of the staircase encoded bits can bypass the inner code. The number of required inner soft-decision decoders can thus be reduced, thereby saving computational complexity. The proposed MLC scheme simultaneously offers up to a 53.7% reduction in the number of inner decoders and up to 0.55 dB of performance improvement when compared with the similar BICM approach.

Decoding of FEC (forward error correction) for optical communication beyond 1 Tb/s is investigated. A configurable single FPGA solution is presented having configurations supporting bit-rates in the range from 40 Gb/s to 1.6 Tb/s. The design allows for trade-offs of bit-rate, footprint, and latency within the resources of the FPGA. A proof-of-concept lab experiment at 40 Gb/s was conducted and pre-FEC — post-FEC performance validated with simulated results.