This paper presents an adversarial jamming attack detection method using energy-detection-based hardware for wireless Internet of Things (IoT) systems. The proposed method utilizes accurate RF signal energy level detection to establish a learning baseline for identifying different types of jamming attacks in wireless networks, which are often characterized by changes in RF energy levels. An adaptive threshold-based binary classification algorithm is implemented to use the detected signal’s energy level as the classification metric. This enables the detection of deceptive/reactive and periodic jamming attacks. Energy levels of RF signal are measured using an ultra-low power (ULP) direct RF-to-digital Received Signal Strength Indicator (RSSI) circuit, developed in a 65-nm CMOS technology, which consumes only 6 nW of power. Further, the RSSI circuit incorporates a band-pass response to filter out ambient signal in the network, providing resilience against continuous RF jammers. Furthermore, a system-level model of the proposed method is presented to demonstrate its detection capabilities. To mitigate the stochastic effects of the wireless channel, a minimum mean-square error (MMSE) channel equalizer is integrated, which improves the detection accuracy by reducing the attack detection error by 21.6%. The RF transmission packet structure is modeled based on the IEEE 802.15.4 protocol. We conducted extensive over-the-air measurements under various attack modalities and scenarios using universal software radio peripheral (USRP) B210 software defined radios (SDRs) to validate the detection accuracy of our proposed hardware-based detection method for energy-constrained IoT systems at 915 MHz. Measurement results demonstrate an accuracy of 96.4% for detecting deceptive jammer and periodic jammer, closely aligning with the simulation results.

Analog circuits remain vulnerable to different types of supply chain attacks including piracy, overproduction, counterfeiting, and reverse engineering. In this article, we present switch mode time domain locking (SMDL) technique to protect analog circuits. This technique integrates a locking mechanism into the time-domain functionality of the circuit. It uses random-key-based switching phases for analog circuits instead of fixed clocks that are conventionally used. The random switching phases are dependent on a key which can be made arbitrarily long. A correct key (CK) with correct alignment of phases can unlock circuit functionality. The locking technique can be applied to a variety of switch-mode analog circuits such as filters, amplifiers, regulators, among others. We implemented this technique on a folded cascode amplifier (FCA) and on a switched-capacitor bandgap reference (BGR) circuit. In both techniques, we employ a 128-bit key to lock the circuit functionality. The design is implemented in a 65-nm CMOS technology. An incorrect key (IK) introduces almost 100% variation in the circuit functionality, ensuring high level of security.

This article presents a closed-loop frequency and phase correction technique for distributed beamforming to maximize the wireless radio frequency (RF) power transfer from multiple energy transmitters (TX) to an Internet of Things (IoT) device receiver (RX). A mathematical analysis of the received power loss due to frequency and phase offset that exists between the transmitters, is used to establish a design methodology for frequency and phase correction among the n-transmitters. Our analysis quantifies the received signal power in the presence of frequency and phase offsets and shows that an optimal frequency and phase correction can boost the combined signal strength by a factor of$n^{2}$from n-transmitters. Further, we present optimal conditions which can expedite the phase offset correction implemented using the one-shot phase correction algorithm. Finally, we validate our frequency and phase offset correction technique to demonstrate a 9.5 dB improvement in received power from three transmitters using universal software radio peripheral (USRP) devices and commercial rectifier at 2.4 GHz for a distance of 3.3 feet between TX and RX. Our proposed closed-loop correction technique utilizes backscatter communication between TX and RX, which improves the energy efficiency of the distributed beamforming system.

Cognitive communication utilizes transient openings in the spectrum to communicate opportunistically, which is a promising technique to enable more efficient spectrum usage in an increasingly congested spectrum environment. We aim to address two main challenges associated with cognitive communication: (i) spectrum sensing should be fast and energy efficient for processing a large bandwidth in a short time; (ii) the spectrum sensing approach should be able to simultaneously recognize multiple signals that are present. In this paper, we propose to address these challenges with a novel design framework that consists of a fast on-chip spectrum sensing in conjunction with a novel learning-based spectrum analysis model at the edge to enhance the optimizations for spectrum agility. We first utilize a model of a programmable analog-based high-quality factor (Q) on-chip spectrum sensor that is capable of scanning the sub-6 GHz band to detect the spectrum usage in less than 1μs. The proposed spectrum sensor also enhances the energy efficiency of the sensing. To complement the onchip spectrum sensor, a deep learning (DL) model is deployed for a fine-grained signal detection between channels in the 400 MHz to 6 GHz range, which is intended to be executed on edge devices. Simulation results show that the DL model can detect multiple different modulated signals with a mean Intersection-over-Union (IoU) of 86.8% in highly-variable bandwidth and center frequency scenarios. Finally, we present a system-level model of our framework to demonstrate the spectrum sensing and classification in the sub-6 GHz frequency band.

In this work, we propose a passive radio frequency (RF) front-end tailored for wake-up receivers (WuRx) to be deployed in cellular Internet of Things (IoT) devices and wearables networks, featuring a low radiation resistance antenna and a high-$Q$matching network implemented with microacoustic resonators integrated to obtain a systematic higher node’s sensitivity at no cost in terms of power consumption. We show how these components can be co-designed to obtain high passive voltage gain, hardware-level blocker immunity, and increased resilience to integration parasitics, relaxing link budget for low-power IoT nodes. We report experimental validation of a PCB antenna with 2-dBi gain measured on an 11-$\Omega $input resistance at resonance, and an in-house fabricated micro-electro-mechanical system (MEMS) thin-film aluminum nitride bulk acoustic resonator with a quality factor$Q=550$and a piezoelectric coupling coefficient$k_{t}^{2} = \mathrm {7~ \%}$, hybridly integrated with a commercial off-the-shelf low-power WuRx circuit to benchmark the proposed RF front-end design at 850 MHz. We demonstrate a passive voltage gain of 12 dB due to the MEMS resonator, and an additional 11 dB due to the proposed antenna design (for a total of an unprecedented 2-dB passive gain in this frequency range) leading to an over the air −61-dBm minimum detectable input power and 23-dB blocker rejection.

This paper presents a new technique of radio frequency (RF) signal strength detection with a received signal strength indicator (RSSI) circuit which can be deployed in an internet-of-things (IoT) network. The proposed RSSI circuit is based on a direct conversion of RF to digital code indicating the signal strength. The direct conversion is achieved by the repeated switching of a rectifier's output voltage using an ultra-low power comparator. A 5-bit programmable feedback circuit is used to correct detection inaccuracies. The RSSI circuit is implemented in a 65-nm CMOS process and consumes 6nW power. It has a linear dynamic range of 26dB and exhibits an error of ±0.5dB with a wide bandwidth of 750MHz. A detailed analysis of the RSSI circuit is presented and verified with simulation and measurement results. The high detection accuracy with ultra-low power consumption of our RSSI circuit is favourable for IoT applications including localization, beamforming, hardware security and other low-power applications.

This article presents large delay-based analog Trojan circuits, a new class of analog Trojans that can be interfaced with digital and analog macros to launch fabrication-time hardware attacks. Two different circuit topologies of analog Trojan are presented, which can generate a delayed trigger output after two days and 60 ms, respectively, when implemented in 65-nm CMOS technology. The large delay is achieved using the transistor's gate-oxide leakage current or a diode's reverse saturation current in combination with the Miller capacitance-based circuits. The proposed analog Trojans can operate across multiple on-chip power domains and can be launched without any digital input signal, making their detection challenging. They show very limited variation in side-channel parameters, which makes them harder to detect through side-channel analysis. In addition, the proposed designs have a small area footprint of 55.5 μm2and 28 μm2, respectively, and can be easily concealed on-chip. We also demonstrate an attack launched using these Trojans to construct a “kill-switch” that disables the power management unit of an IC. Process and temperature variations were also investigated to assess their impact on the design. We implemented the thick-oxide gate leakage modeling to study the robustness of the proposed Trojan design. We also present the long-term potential threat of these Trojans where the output trigger signal is generated after an even larger delay.