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Corentin Ferry

dblp:204/3472 · DBLP profile ↗
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2ranked-venue papers
1as first author
1since 2021 · last 2023
0000-0002-6284-7210ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 67% Reconfigurable computing and FPGAs · 33%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs
FPGA accelerator
0.712023
Increasing FPGA Accelerators Memory Bandwidth With a Burst-Friendly Memory Layout · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
Memory systems › memory bandwidth
memory bandwidth optimization
0.712023
Increasing FPGA Accelerators Memory Bandwidth With a Burst-Friendly Memory Layout · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
Memory systems
memory layout
0.712023
Increasing FPGA Accelerators Memory Bandwidth With a Burst-Friendly Memory Layout · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
Compilers and program optimization › program transformation
source-to-source transformation
0.212023
Increasing FPGA Accelerators Memory Bandwidth With a Burst-Friendly Memory Layout · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023

Methods — techniques the papers use, named apart from their topics

tiling · 1.3burst transfer · 1.3
YearPublicationVenuePosition
2023 Increasing FPGA Accelerators Memory Bandwidth With a Burst-Friendly Memory Layout
abstract
Offloading compute-intensive kernels to hardware accelerators relies on the large degree of parallelism offered by these platforms. However, the effective bandwidth of the memory interface often causes a bottleneck, hindering the accelerator’s effective performance. Techniques enabling data reuse, such as tiling, lower the pressure on memory traffic but do not fully exploit the bandwidth. A further increase in bandwidth utilization is possible by using burst rather than element-wise accesses, provided the data is contiguous in memory. In this article, we propose a memory allocation technique, and provide a proof-of-concept source-to-source compiler pass, that enables such burst transfers by modifying the data layout in external memory. Our experiments show the new memory allocation yields close to 100% bandwidth utilization while the memory engines occupy less than 5% of the field-programmable gate array (FPGA) logic area.
Corentin Ferry, Tomofumi Yuki, Steven Derrien, Sanjay V. Rajopadhye
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2017 Hardware and software for reproducible research in audio array signal processing
abstract
In our demo, we present two hardware platforms for prototyping audio array signal processing. Pyramic is a 48-channel microphone array fitted on an FPGA and Compact Six is a portable microphone array with six microphones, closer to the technical constraints of consumer electronics. A browser based interface was developed that allows the user to interact with the audio stream from the arrays in real time. The software component of this demo is a Python module with implementations of basic audio signal processing blocks and popular techniques like STFT, beamforming, and DoA. Both the hardware design files and the software are open source and freely shared. As part of a collaboration with IBM Research, their beamforming and imaging technologies will also be portrayed. The hardware will be demonstrated through an installation processing the microphone signals into light patterns on a circular LED array. The demo will be interactive and let visitors play with different algorithms for DoA (SRP, FRIDA [1], Bluebild) and beamforming (MVDR, Flexibeam [2]). The availability of an open platform with reference implementations encourages reproducible research and minimizes setup-time when testing and benchmarking new audio array signal processing algorithms. It can also serve as a useful educational tool, providing a means to work with real-life signals.
Eric Bezzam, Robin Scheibler, Juan Azcarreta, Hanjie Pan, Matthieu Simeoni, Rene Beuchat, Paul Hurley, Basile Bruneau, Corentin Ferry, Sepand Kashani
ICASSP9