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Gary Bronner

dblp:205/0237 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2017
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 61% Emerging computing paradigms · 30% Integrated circuit design · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Emerging computing paradigms
neuromorphic computing
0.312017
Resistive Random Access Memory for Future Information Processing System · Proc. IEEE 2017
Memory systems
non-volatile memory
0.312017
Resistive Random Access Memory for Future Information Processing System · Proc. IEEE 2017
Memory systems › non-volatile memory
resistive memory
0.312017
Resistive Random Access Memory for Future Information Processing System · Proc. IEEE 2017
Integrated circuit design
device-circuit co-design
0.112017
Resistive Random Access Memory for Future Information Processing System · Proc. IEEE 2017

Methods — techniques the papers use, named apart from their topics

device-circuit co-design · 0.3
YearPublicationVenuePosition
2017 Resistive Random Access Memory for Future Information Processing System
abstract
Resistive random access memory (RRAM) is regarded as one of the most promising emerging memory technologies for next-generation embedded, standalone nonvolatile memory (NVM), and storage class memory (SCM) due to its speed, density, cost, and scalability. Considerable progress has been made in recent years on the manufacturability of RRAM, with low-density RRAM products now in production and the path to higher density parts becoming clearer. This review updates the learning on the fundamental materials and process integration needed for high-volume manufacturing and summarizes very recent progress on array level performance improvement methodology using novel techniques, and circuit level contributions for different applications. The device performance, array integration, and device/circuit codesign for memory systems are discussed. Novel applications besides embedded memory and standalone memory are addressed, including hardware security, neuromorphic computing, and nonvolatile logic systems.
Huaqiang Wu, Xiao Hu Wang, Bin Gao 0006, Ning Deng 0008, Zhichao Lu, Brent Haukness, Gary Bronner, He Qian
Proc. IEEE7