Moore’s law is reaching saturation, while the demand for computing capacity continues to rise. Application-Specific Instruction-Set Processors (ASIPs) are therefore an essential technology for embedded processing in areas such as communication, media, gaming, and control systems, due to their high area and energy efficiency. The most effective method for ASIPs acceleration is known as instruction fusion. Instruction fusion enhances performance but also introduces challenges related to the complexity of structural hazard control. The difficulty in this research field is achieving fine-grained structural hazard control using low-cost hardware. The state-of-the-art technologies have not been able to effectively address this challenge. Firstly, this paper systematically analyzes the rationale behind instruction fusion and explores methods to optimize its performance. Secondly, based on the design of a 5G micro-base station baseband processor, we present an instruction fusion pipeline design example. Furthermore, to address the structural hazards that arise from instruction fusion, we propose a lightweight Hardware Resource Table (HRT) to address the issue and outline its benefits. These benefits include utilizing low silicon costs to achieve performance improvements and reducing on-chip program memory. According to benchmark evaluations, area efficiency improves by 23%, accompanied by a 108% increase in energy efficiency.