An essential goal of the static random access memory (SRAM) array termination design is to both terminate as well as maintain a homogeneous environment for the active edge cells in the array. Local layout effects (LLEs) in the array termination design can exert influence on the active array SRAM devices in close proximity to the termination region, which can lead to undesirable inhomogenuities in the array. The impact of LLEs, originating from the array termination design, on SRAM read performance and Vminfail count, are examined using a 14nm FinFET technology. Large-scale SRAM read performance statistics are analyzed to identify elevated read currents and low-voltage fail counts associated with the array termination. The root cause and modulating factors are explored, and potential solution paths are discussed.