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Sohum Datta

dblp:205/4087 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2020
0000-0001-9546-6927ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Emerging computing paradigms · 50% Reconfigurable computing and FPGAs · 50%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs › reconfigurable computing
FPGA-based machine learning accelerators
0.412020
QuantHD: A Quantization Framework for Hyperdimensional Computing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Emerging computing paradigms › neuromorphic computing
hyperdimensional computing
0.412020
QuantHD: A Quantization Framework for Hyperdimensional Computing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020

Methods — techniques the papers use, named apart from their topics

ternary quantization · 0.4quantization · 0.4binarization · 0.4
YearPublicationVenuePosition
2020 QuantHD: A Quantization Framework for Hyperdimensional Computing
abstract
Brain-inspired hyperdimensional (HD) computing models cognition by exploiting properties of high dimensional statistics-high-dimensional vectors, instead of working with numeric values used in contemporary processors. A fundamental weakness of existing HD computing algorithms is that they require to use floating point models in order to provide acceptable accuracy on realistic classification problems. However, working with floating point values significantly increases the HD computation cost. To address this issue, we proposed QuantHD, a novel framework for quantization of HD computing model during training. QuantHD enables HD computing to work with a low-cost quantized model (binary or ternary model) while providing a similar accuracy as the floating point model. We accordingly propose an FPGA implementation which accelerates HD computing in both training and inference phases. We evaluate QuantHD accuracy and efficiency on various real-world applications, and observe that QuantHD can achieve on average 17.2% accuracy improvement as compared to the existing binarized HD computing algorithms which provide a similar computation cost. In terms of efficiency, QuantHD FPGA implementation can achieve on average 42.3× and 4.7× (34.1× and 4.1×) energy efficiency improvement and speedup during inference (training) as compared to the state-of-the-art HD computing algorithms.
Mohsen Imani, Samuel Bosch, Sohum Datta, Sharadhi Ramakrishna, Sahand Salamat, Jan M. Rabaey, Tajana Rosing
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3