Exponentiation in finite fields is an essential operation used in many applications ranging from error control coding to cryptographic computations, while representation in Gaussian normal basis (GNB) offers low complexity arithmetic, especially in hardware architectures. In this article, we propose several new hardware architectures for binary exponentiation in GNB. The proposed architectures make use of different levels of precomputation and the efficient digit-level parallel-in parallel-out, and hybrid-double multipliers. We support our new designs with novel countermeasures against side-channel analysis that require minimal implementation overhead. Moreover, we obtain implementation results for all architectures and provide realistic and fair comparisons with the previously known works available in the literature. It is shown that our newly proposed architectures outperform the existing hardware architectures in terms of area and time complexities and security.

The multiplicative inverse over binary fields is one of main arithmetic operations used in cryptography. This paper presents two new inversion architectures. First, an improved architecture for classic inversion scheme using single multiplier is presented. The new improved inverter achieves lower latency through loading input registers during last multiplication cycle, at the expense of higher propagation delay. After this, a novel inversion architecture which uses half the latency to process the classic-based addition chains (or improved ones) is presented. The latter architecture, named Classical-Interleaved, is constructed based on a novel fully-serial-in square-multiply processor (FSISM). The FSISM, squares one operand, and multiply it to the second one, concurrently while the two inputs are absorbed serially digit-by-digit. The new classical inverter and the new classical-interleaved inverter reduce the latency compared to other schemes. In addition, the proposed classical and interleaved inverters outperform the original Itoh-Tsujii algorithm (ITA) and Ternary Itoh-Tsujii / optimal 3-chain algorithms in terms of its higher throughput and improved hardware efficiency for a number of digit sizes. The efficiency of the proposed field inverters are demonstrated by comparisons based on application specific integrated circuits (ASIC) implementations results using the standard 65 nm CMOS technology libraries.

Itoh and Tsujii proposed a fast algorithm for computing multiplicative inverses (inversions) over GF(2m) using normal bases by iterating single multiplications and cyclic shifts. Recently, the Itoh-Tsujii algorithm (ITA) has been modified to use two digit-level single multiplications. The improvements of the modified Itoh-Tsujii and its variant algorithms are based on reducing the computational latency at the expense of more area requirements. In this paper, we propose a new inversion architecture based on the classical IT algorithm (or improved one) utilizing a novel interleaved computations of two single multiplications and squarings at the digit-level. The new inverter outperforms previous modified Itoh-Tsujii algorithms (such as the Ternary Itoh-Tsujii and optimal 3-chain algorithms) in terms of its lower latency, higher throughput, and improved hardware efficiency. The efficiency of the proposed field inverter is demonstrated by comparisons based on application specific integrated circuits (ASIC) implementations results using the standard 65nm CMOS technology libraries.