VLDB 2026 Research / reviewers in the wild / expert
Stefan Bodenmüller
dblp:205/6084
· DBLP profile ↗
9ranked-venue papers
3as first author
6since 2021 · last 2025
0000-0002-4596-2305ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 8 · 2 first-author · 5 since 2021Theory of computation · 6 · 2 first-author · 4 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Verification of forward simulations with thread-local, step-local proof obligationsabstractThis paper presents a proof technique for proving refinements for general state-based models of concurrent systems that reduces proving forward simulations to thread-local, step-local proof obligations. The approach has been implemented in our theorem prover KIV, which translates imperative programs to a set of transition rules and generates proof obligations accordingly. Instances of this proof technique should also be applicable to systems specified with ASM rules, B events, or Z operations. To exemplify the proof methodology, we demonstrate it with two case studies. The first verifies linearizability of a lock-free implementation of concurrent hash sets by showing that it refines an abstract concurrent system with atomic operations. The second applies the proof technique to the verification of opacity of Transactional Mutex Locks (TML), a Software Transactional Memory algorithm. Compared to the standard approach of proving a forward simulation directly, both case studies show a significant reduction in proof effort. Gerhard Schellhorn, Stefan Bodenmüller, Wolfgang Reif |
Sci. Comput. Program. | 2 |
| 2024 | VeriCode: Correct Translation of Abstract Specifications to C Code
Gerhard Schellhorn, Stefan Bodenmüller, Wolfgang Reif |
IFM | 2 |
| 2024 | A Fully Verified Persistency Library
Stefan Bodenmüller, John Derrick, Brijesh Dongol, Gerhard Schellhorn, Heike Wehrheim |
VMCAI (2) | 1 |
| 2023 | Refinement and Separation: Modular Verification of Wandering Trees
Gerhard Schellhorn, Stefan Bodenmüller, Wolfgang Reif |
iFM | 2 |
| 2023 | Thread-Local, Step-Local Proof Obligations for Refinement of State-Based Concurrent Systems
Gerhard Schellhorn, Stefan Bodenmüller, Wolfgang Reif |
ABZ | 2 |
| 2022 | Verification of Crashsafe Caching in a Virtual File System SwitchabstractWhen developing file systems, caching is a common technique to achieve a performant implementation. Integrating write-back caches is not primarily a problem for functional correctness, but is critical for proving crash safety. Since parts of written data are stored in volatile memory, special care has to be taken when integrating write-back caches to guarantee that a power cut during a running operation leads to a consistent state. This article shows how non-order-preserving caches can be added to a virtual file system switch (VFS) and gives a novel crash-safety criterion matching the characteristics of such caches. Broken down to individual files, a power cut can be explained by constructing an alternative run, where all writes since the last synchronization of that file have written a prefix. VFS caches have been integrated modularly into Flashix, a verified file system for flash memory, and both functional correctness and crash-safety of this extension have been verified with the interactive theorem prover KIV. Stefan Bodenmüller, Gerhard Schellhorn, Wolfgang Reif |
Formal Aspects Comput. | 1 |
| 2020 | Modular Integration of Crashsafe Caching into a Verified Virtual File System Switch
Stefan Bodenmüller, Gerhard Schellhorn, Wolfgang Reif |
IFM | 1 |
| 2018 | Symbolic execution for a clash-free subset of ASMs
Gerhard Schellhorn, Gidon Ernst, Jörg Pfähler, Stefan Bodenmüller, Wolfgang Reif |
Sci. Comput. Program. | 4 |
| 2017 | Modular Verification of Order-Preserving Write-Back Caches
Jörg Pfähler, Gidon Ernst, Stefan Bodenmüller, Gerhard Schellhorn, Wolfgang Reif |
IFM | 3 |