Compliance with design rule constraints constitutes a fundamental prerequisite for successful fabrication in advanced integrated circuit design. As foundries progressively introduce process-specific customization for better performance, new design rule challenges emerge across the device layers, such as implant layer constraints in the designs with multiple threshold voltages, and the trim poly layer constraints in the self-aligned double patterning (SADP). Conventional methodologies typically address such topological constraints in the legalization stage. In addition, filler insertion during chip finishing serves to improve manufacturability, such as a more uniform chip surface and a more robust power integrity. However, improper filler insertion might undermine the previous legalized layout. This work presents a co-optimization framework in the legalization and filler insertion stage, adaptable to multi-layer constraint scenarios. We model the filler insertion problem as a multi-branch tree and develop a dynamic programming-based pre-pruning algorithm, which is also able to detect violations in the legalization stage. To reduce runtime, two violation detectors are introduced for legalization, including a look-up table (LUT) inference method and a greedy scanning algorithm. These components are systematically integrated into a co-optimization framework, with configurable parameterization to ensure scalability across diverse constraints. Experimental results show that our algorithm can significantly reduce the number of violations compared with state-of-the-art work and the commercial tool.

Legalization holds significant importance in VLSI physical design, as it significantly influences the manufacturability and reliability of circuits. Recently, advanced foundry nodes introduced complex constraints in standard-cell legalization, which makes legalization even harder. In this paper, we develop a legalization framework with design rule constraints enhanced by Monte-Carlo-Based cell priority optimization. We first handle abnormal density distribution to reduce the subsequent legalization’s hardness. Then, we propose an interval-assisted sequential legalization algorithm considering multiple design rule constraints with a Monte-Carlo-Based cell priority decision technique. Besides, based on the characteristics and complexity of different design rule constraints, we present a refinement phase to handle the remaining design rule constraints with corresponding detectors. Compared with a leading commercial tool, experiments on industrial benchmarks show that our legalization framework achieves 11% smaller average displacement, 15% smaller maximum displacement, 1.63× speedup, and 13% fewer remaining design rule violations on average.

Adherence to design rule constraints, a cornerstone principle of Design for Manufacturability (DFM), is essential for ensuring successful fabrication in modern circuit design. As the foundries keep introducing more customization for better performance, new design rule challenges emerge with the device layers, such as implant layer constraints in the designs with multiple threshold voltages, and the trim poly layer constraints in the self-aligned double patterning (SADP). These constraints are typically tackled in the legalization stage. In addition, during the chip finishing, fillers are inserted for better manufacturability, such as a more uniform chip surface and a more robust power integrity. However, improper filler insertion might undermine the previous legalized layout. This paper presents a co-optimization framework in the legalization and filler insertion stage, which is extensible for other layer constraints. We model the filler insertion problem as a multi-branch tree and present a dynamic programming-based pre-pruning algorithm, which is also able to detect violations in the legalization stage. To reduce runtime, we additionally propose two violation detectors for legalization based on the look-up table (LUT) inference and greedy algorithm. Experimental results show that our filler insertion algorithm can significantly reduce the number of violations compared with state-of-the-art work. With our violation detectors in legalization, the co-optimization framework achieves better performance compared with the commercial tool.

A growing recognition of potential vulnerabilities to layout-level Hardware Trojan (HT) attacks has spurred significant research efforts aimed at enhancing the resilience of ICs against such threats. However, traditional hardware security has been predominantly concerned with defensive measures, often overlooking the original key metrics in physical design evaluation: power, performance, and area (PPA). This study introduces an automated methodology incorporating HT considerations into the practical physical design process. Utilizing a Bayesian optimization framework, it effectively navigates the operation of commercial physical implementation tools in the solution space of hyper-parameter settings. Innovative strategies inspired by mosaic techniques, such as cell shifting and buffer insertion, realize additional improvements in layout-level trojan prevention. Comparative evaluations have shown that our approach outperforms leading entries from the ISPD 2023 Contest in terms of PPA and HT prevention metrics, thereby providing significant insights into the synergy between these critical factors.

In modern circuits, mixed-cell-height standard cells have been prevailing to meet various requirements and achieve better trade-offs among timing, power, and routability. Besides, the constraints of the minimum-implant-area (MIA) and drain-to-drain-abutment (DDA) arise as emerging challenges at advanced technology nodes. In this paper, we present an algorithm to address the mixed-cell-height placement problem with MIA and DDA constraints in three major stages: (1) post-global placement, (2) legalization, and (3) detailed placement. In the post-global stage, we first align mixed-cell-height standard cells to the desired rows by conjugate gradient method with dynamic step size and then reorder them by the shortest path algorithm to distribute the source nodes evenly. In the legalization stage, we propose a two-step combination algorithm to cluster cells and repack the clusters to minimize the wirelength, after which we presented a queue based method to address the inter-row MIA violations. In the detailed placement, an MIA-aware DDA reduction algorithm is adopted after multi-region partitioning to eliminate DDA violations without introducing MIA violations. Experimental results show that our algorithm can resolve all MIA and almost all DDA violations with a 13% reduction in displacement, a 4% reduction in HPWL, and 25% less runtime compared with the state-of-the-art work.

Modern circuits often contain standard cells of different threshold voltages (multi-VTs) to achieve a better trade-off between timing and power consumption. Due to the heterogeneous cell structures, the multi-VTs cells impose various implant layer constraints, further complicating the already time-consuming filler cell insertion process. In this paper, we present a fast and near-optimal algorithm to solve the filler insertion problem with complex implant layer rules and minimum filler width constraints. We first propose an inference-driven detecting algorithm to identify each design rule violation accurately. Then, a dynamic-programming-based insertion method is developed to reduce the implant layer violations. Finally, we design a contour-driven violation refinement strategy to further improve manufacturability. Experimental results show that our algorithm can reduce the number of violations significantly compared with state-of-the-art works. Besides, with our identifier in the legalization stage, we can avoid conflicts in advance and solve almost all violations after filler insertion in industrial cases.