As network line rates continue to escalate, sketch-based methods have become increasingly pivotal tools in network measurement. Traditional sketch-based measurements are performed in fixed windows, which leads to truncation of network traffic and results in issues of underreporting. Recently, some studies have introduced the sliding window model into sketch-based measurements, providing a promising solution to this problem. However, these methods require the deployment of multiple sketch instances on a network equipment, consuming substantial memory resources. In addition, they necessitate complex data collection operations to achieve high accuracy. In this paper, we propose a novel network measurement framework, namely Round Sketch, which minimizes memory usage by incorporating an indicator into each counter and simplifies the data collection process by providing an efficient collection-and-set operation. Furthermore, Round Sketch is generic and can be applied to a wide range of existing sketches. We have implemented Round Sketch on FPGA platform and conducted comprehensive evaluations based on various measurement tasks. The results indicate that Round Sketch achieves comparable accuracy to state-of-the-art solutions while occupying only half of the memory space.

Intelligent traffic analysis, serving as a core enabler of QoS (Quality of Service) policies, plays a pivotal role in finegrained resource scheduling and mission-critical performance assurance. While SmartNIC-based data plane offloading effectively alleviates host processing burdens, existing solutions lack a unified traffic management capability, restricting them to packet-level classification or inference model acceleration. This paper proposes FlowAccel, an end-to-end hardware architecture for line-rate intelligent network traffic analysis in FPGA-based SmartNICs. FlowAccel constructs a hierarchical memory structure for real-time updates of flow state and per-flow packet length sequence. Its feature extraction pipeline enables parallel computation of traffic fingerprint features and incorporates a dedicated XGBoost acceleration engine for hardware-optimized model inference. Implemented on the Alveo U50, our prototype demonstrates a$1.08 \mu ~\mathrm{s}$median inference latency under 100 Gbps network traffic. Compared with a single-logical-core DPDK software implementation, FlowAccel achieves a$54 \times$latency reduction and$180 \times$throughput improvement. In terms of accuracy, FlowAccel attains Macro-F1 scores of$89.0 \%, 86.3 \%$, and 92.4 % across three public datasets, significantly outperforming existing single-port 100 Gbps hardware offloading approaches.

Expanding the input bandwidth of the human-machine interface to capture more control intentions from the human is key to achieving dexterous control of multi-degree-of-freedom prosthetic hands/wrists. This paper presents a wearable intelligent prosthesis system based on multimodal fusion, which integrates voice interaction, myoelectric control, limb movement decoding, and computer vision-based environmental perception. The system supports intention estimation throughout the entire process from grasping to operation, enabling synchronized control of 4 grasp gestures and 2 wrist DOFs. Moreover, all these decisions are made automatically during the user’s natural and continuous body movements. Six able-bodied subjects and two amputee subjects participated in a comparative experiment involving multi-object grasping and operation in a cluttered environment. Compared to myoelectric pattern recognition, our method demonstrated significant advantages in improving grasp and operation efficiency (reducing total time, grasp time, and operation time by 67.62%, 67.89%, and 67.40% for able-bodied subjects, and by 73.93%, 69.82%, and 76.67% for amputees). It also reduced control burden, with gesture and wrist myocontrol times decreasing by 71.77% and 100% in able-bodied subjects, and by 80.59% and 100% in amputees. These advantages are not limited to the grasp object, grasp part, operation type, or the subject involved. Compared to other semi-autonomous control methods, our method achieved a higher reduction in time metrics, with reduction rates ranging from 22.61% to 84.82% higher, resulting in a more significant performance improvement. Furthermore, the questionnaire showed that the system was well-recognized by the subjects in terms of operational robustness, wearing comfort, and user experience.

In an era of rapidly increasing network speeds and expanding infrastructures, the demand for real-time and accurate network measurement tasks by network management has progressively heightened. Among these tasks, heavy flow detection has received sustained attention due to its broad application in areas such as traffic scheduling and congestion control. Concurrently, as a growing number of network services are deployed to the data plane, the already scarce resources of the data plane face even stricter constraints in multi-task scenarios. Hence, this paper proposes a heavy flow detection method aimed at resource-constrained scenarios, implementing a lightweight and hardware-software integrated real-time heavy flow detection on a data plane based on FPGA programmable switches. By designing an accurate flow table utilizing FPGA resource characteristics and optimizing the implementation of the sketch algorithm in hardware, our method significantly reduces the resource overhead of the data plane while conducting real-time detection of large network flows. Tests conducted with different real network traffic and a 4×10Gbps programmable network card have demonstrated that, with minimal hardware resources and minimal interference with network forwarding services, the real-time heavy flow detection precision of our method can reach more than 97%.