This paper presents a bioinspired, multi-channel auditory signal encoder based on volatile memristors, designed to mimic the short-term adaptation behavior of the human auditory system. The system integrates a threshold generator with an asynchronous delta modulator (ADM) to dynamically adjust threshold voltages based on real-time memristor behavior. The encoder is implemented with standard 130nm CMOS technology, occupying a compact area of 0.44 mm × 0.185 mm per channel and consuming 299.85 μW per channel. The adaptive resolution of the encoder is validated in simulations using a memristor model derived from real device data, demonstrating adaptive output firing rates as a result of memristor resistance volatility. With a maximum delay of 45.25 ns for a 1 kHz sound input, the design is well-suited for spike-domain neuromorphic systems.

In this demonstration, we present a hardware/software co-design methodology for Convolutional Neural Networks, where the classification section is managed through Resistive RAMs (RRAMs). To this aim, RRAM arrays are mounted onto the ArC TWO instrumentation board, which is interfaced to a laptop. A software Python front-end executes convolutional layers for feature extraction, generates stimuli for RRAMs, and controls the instrumentation board. As a proof of concept, handwritten digits classification is exhibited.

Memristors have shown promising features for enhancing neuromorphic computing concepts and AI hardware accelerators. In this paper, we present a user-friendly software infrastructure that allows emulating a wide range of neuromorphic architectures with memristor models. This tool empowers studies that exploit memristors for online learning and online classification tasks, predicting memristor resistive state changes during the training process. The versatility of the tool is showcased through the capability for users to customise parameters in the employed memristor and neuronal models as well as the employed learning rules. This further allows users to validate concepts and their sensitivity across a wide range of parameters. We demonstrate the use of the tool via an MNIST classification task. Finally, we show how this tool can also be used to emulate the concepts under study in-silico with practical memristive devices via appropriate interfacing with commercially available characterisation tools.

Mass characterisation of emerging memory devices is an essential step in modelling their behaviour for integration within a standard design flow for existing integrated circuit designers. This work develops a novel characterisation platform for emerging resistive devices with a capacity of up to 1 million devices on-chip. Split into four independent sub-arrays, it contains on-chip column-parallel DACs for fast voltage programming of the DUT. On-chip readout circuits with ADCs are also available for fast read operations covering 5-decades of input current (20nA to 2mA). This allows a device’s resistance range to be between 1k$\Omega$ and 10M$\Omega$ with a minimum voltage range of ±1.5V on the device.

Memristive technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate the behaviour of our in-house fabricated custom memristor model and its integration into the Cadence Electronic Design Automation (EDA) tools for verification. Various input stimuli were given to record the memristive device characteristics both at the device level as well as the schematic level for verification of the memristor model. This design flow from device to industrial level EDA tools is the first step before the model can be used and integrated with Complementary Metal-Oxide Semiconductor (CMOS) in applications for hybrid memristor/CMOS system design.

The capability of in-memory computation, reconfigurability, low power operation as well as multistate operation of the memristive device deems them a suitable candidate for designing electronic circuits with a broad range of applications. Besides, the integrability of memristor with CMOS enables it to use in logic circuits too. In this work, we demonstrate with examples the design flow for memristor-based electronics, after the custom memristor model already being integrated and validated into our chosen Computer-Aided Design (CAD) tool to performing layout-versus-schematic and post-layout checks including the memristive device. We envisage that this step-by-step guide to introducing memristor into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with memristive-enhanced systems.

A methodology is introduced here to exploit the programmability of the memristors in order to realize reconfigurable monolithic analogue circuit elements. Classical network synthesis methods are used to synthesize adjustable active inductors with inductance values exceeding those of on-chip passives by several orders of magnitude. In this paper, a wide range of active inductance values are obtained by employing memristor to control the biasing current of operational transconductance amplifiers used to implement gyrators. The gyration constant of the proposed gyrator will be linearly controlled by memristance state. The implementation of the designed circuit is realized in 0.18μm commercially available complementary metal-oxide-semiconductor (CMOS) technology from TSMC. Circuit performance is simulated using Cadence Virtuoso. The utilized off-chip memristor is a metal-oxide bi-layer memristor which exhibits a non-volatile memristance range of 4.7kΩ to 170kΩ. The active inductance range achieved is from approximately 95μH to 1.55mH with an inductive bandwidth of 69MHz and 18MHz respectively. The total power consumption is between 0.21mW to 1.95mW depending on the memristance and equivalent inductance.

We demonstrate an environmental control system for testing Resistive Random Access Memory technologies under accurately controlled humidity and temperature. The demonstrated system compresses the functionality of existing environmental control systems into a low cost, desktop-size solution, aimed at providing results quickly and with minimum installation and running overheads.

Environmental conditions can greatly affect the performance of semiconductor devices. Great sophistication has thus gone into developing versatile systems that allow benchmarking of operating characteristics under a variety of temperature and humidity conditions. Recently, Resistive Random Access Memory (RRAM) technologies, also known as memristors, have received a lot of attention for memory and computing applications. This interest is showcased by several reports on technology and applications developments, as well as developments on the underpinning infrastructure, i.e. models and characterization tools, that renders such technologies useful. Several international research groups and companies are nowadays using ArC One™, a versatile instrument that allows en masse characterization of RRAM technologies, as has been presented previously in several demo sessions at ISCAS. In this work, we present a newly developed module that expands ArC One™ capabilities through incorporating an environmental control system. The proposed module condenses the functionality of significantly larger, more complex and higher cost systems into a low cost, small form-factor and user friendly desktop-operated device. The system allows for temperature, atmospheric composition and humidity control and can be used for studying the impact of such settings on the electrical characteristics of RRAM technologies.

With the recent advances of the emerging memories technologies, research are able to implement novel circuits, systems and computer architectures towards the design of high-performance and low-power electronic systems able to accelerate and/or optimize the functionality of many computer workflows. One emerging technology, the ReRAM/memristor is gathering attention due to its inherent advantages for logic and memory computing systems. At the same time, CMOS circuit design seems to have reached a limit, where easily optimized circuit solutions cannot be found. Thus, further research towards novel logic gate families, such as Threshold Logic Gates (TLGs), a logic family known for its high-speed and low power consumption, is needed. Although many implementation concepts of TLG circuit are using memristors, few of these implementations are based on physical ReRAM devices. In this work we are proposing a memristor-based threshold logic gate design towards the optimization of computer workflows. The presented results include a physical implementation of the proposed circuits which supports the concept of memory-based reconfigurable computing circuits and systems.

In this demo we present a comprehensive solution for benchmarking the multibit capabilities of resistive memory cells using sequential programming pulses. The algorithm is presented through a rich graphical user interface that allows the user to fully tune the benchmarking parameters.

In this work we present an evaluation routine aimed towards assessing the multibit capability of Resistive Random Access Memory (RRAM) technologies. We illustrate a characterization methodology for the maximum possible exploitation of the resistive states of a RRAM cell. Our characterization routine consists of a three phase algorithm: during the first it infers the polarity needed to induce a change in the device's conductance; the second stabilizes the resistive states of the device into a baseline resistance and during the third a sequence of pulses of increasing amplitude is used to determine the actual resistive states. This technology-agnostic methodology allows for efficient and high resolution partitioning of the cell's resistive operating range allowing them to operate in a truly analogue fashion. Demonstrating the maximum potential of RRAM cells in terms of closely packed resistive states can open new avenues for research in non-volatile memories, reconfigurable electronics and neuromorphic applications.

The translation of emerging application concepts that exploit resistive random access memory (ReRAM) into large-scale practical systems requires realistic yet computationally efficient device models. Here, we present a ReRAM model, where device current-voltage characteristics and resistive switching rate are expressed as a function of: 1) bias voltage and 2) initial resistive state (RS). The model versatility is validated on detailed characterization data, for both filamentary valence change memory and nonfilamentary ReRAM technologies, where device resistance is swept across its operating range using multiple input voltage levels. Furthermore, the proposed model embodies a window function which features a simple mathematical form analytically describing RS response under constant bias voltage as extracted from physical device response data. Its Verilog-A implementation captures the ReRAM memory effect without requiring integration of the model state variable, making it suitable for fast and/or large-scale simulations and overall interoperable with current design tools.

We demonstrate a desktop platform which has the ability of modeling ReRAM TiO2samples in a highly automated manner. The system consists of a bespoke RRAM characterization instrument that hosts packaged RRAM devices and is operated via a PC. The system's python-based software includes a module that automatically applies strategically chosen sequences of pulses to a test device and then extracts the suitable parameter values for a resistive switching model from the elicited response.