Neuromorphic architectures have been introduced as platforms for energy-efficient spiking neural network execution. The massive parallelism offered by these architectures has also triggered interest from nonmachine learning application domains. In order to lift the barriers to entry for hardware designers and application developers, we present RANC: a reconfigurable architecture for neuromorphic computing, an opensource highly flexible ecosystem that enables rapid experimentation with neuromorphic architectures in both software via C++ simulation and hardware via FPGA emulation. We present the utility of the RANC ecosystem by showing its ability to recreate behavior of IBM’s TrueNorth and validate with a direct comparison to IBM’s Compass simulation environment and published literature. RANC allows optimizing architectures based on application insights as well as prototyping future neuromorphic architectures that can support new classes of applications entirely. We demonstrate the highly parameterized and configurable nature of RANC by studying the impact of architectural changes on improving application mapping efficiency with quantitative analysis based on Alveo U250 FPGA. We present post routing resource usage and throughput analysis across implementations of synthetic aperture radar classification and vector matrix multiplication applications, and demonstrate a neuromorphic architecture that scales to emulating 259K distinct neurons and 73.3M distinct synapses.

We report on the implementation of a path planning algorithm on the TrueNorth neurosynaptic system. Our implementation exploits processing in the temporal domain within the architectural constraints of the TrueNorth chip to deduce the optimal path. The optimal path is computed on the TrueNorth chip for grid maps with dimensions as large as 173 × 168 nodes consuming 70.0mW at an operating voltage of 0.8V.

Physically and computationally efficient hardware coupled with fast sparse approximation solvers provide opportunities for real-time visual processing on low-power embedded platforms. This paper presents a system using the low-power Locally Competitive Algorithm (LCA) on the highly programmable, brain-inspired IBM TrueNorth chip. A small-scale spiking LCA network is successfully implemented on the TrueNorth chip, resulting in node dynamics comparable to that of a discretized LCA network. The sparse representations computed by the LCA implemented on TrueNorth result in minimal reconstruction error for every trial. This performance is achieved using only 11 of the available 4096 cores on the chip, offering the potential for scalability for real-world applications of this system.