This article presents a cryogenic fractional-N 4–5.9-GHz cascaded phase-locked loop (PLL) operating down to 4 K for a transmon control system. The main PLL stage employs a supply-boost constant charging current sampling phase detector (SBCC-SPD) to achieve ultralow rms jitter and fractional spur from 300 to 4 K. The first-stage PLL operates in integer-N mode employing an inverter-based sampling PD and a Class-F voltage-controlled oscillator (VCO) to achieve low output phase noise, with a frequency-tuning range of 11.8–15.9 GHz. The second-stage PLL operates in fractional-N mode using double-multimodule divider (MMD) with shared delta-sigma-modulator (DSM) architecture. It incorporates an SBCC-SPD and Class-B VCO, with a frequency-tuning range of 4–5.9 GHz for transmon control application. The reference signal of SBCC-SPD is from the divided signal of the first-stage PLL, which is modulated by the same DSM used in the feedback path of the second-stage PLL to compensate for the quantization error. Fabricated in a 28-nm Bulk CMOS process, the PLL achieves an rms jitter of 58.8 fs at 300 K and 36.9 fs at 4 K, with a fractional spur of −71.8 dBc at 300 K and −69.1 dBc at 4 K. The chip consumes a power consumption of 24.8 mW at 300 K and 14.2 mW at 4K corresponding to a figure of merit (FOM) of −257.1 dB. This chip occupies an area of 0.344 mm2.

With the increasing demand for large-scale model deployment, cloud-based computing remains indispensable. However, energy and bandwidth overheads in edge-to-cloud data transmission pose significant challenges. This work presents a low-power, multimodal SoC that performs on-chip image and audio compression processing, enabling energy-efficient and low-latency cloud interaction for Internet of Things (IoT) applications. The SoC employs a two-level optimization strategy. At the microarchitecture level, a customized 16-bit fixed-length complex instruction set computing (CISC) microprocessor is introduced. Validated against a RISC-V minimal baseline RV32E equipped with equivalent peripheral engines, the proposed core achieves a$5.06\times $reduction in core logic gate count and up to$2.42\times $improvement in energy efficiency under iso-latency conditions. Additionally, a multipower domain strategy is adopted to further optimize energy efficiency, yielding$5.03\times $and$4.13\times $improvements for image and audio modes, respectively. Fabricated in a 65-nm CMOS process, our SoC integrates both image and audio processing, achieving an ultralow power consumption of 54.1–$387.5~\mu $W. It outperforms state-of-the-art dual-modal processors, achieving a$2.84\times $reduction in image-processing core power and a$12.78\times $reduction in audio compression power. Furthermore, our SoC achieves an energy efficiency of 206 pJ/bit of audio task and 15.5 pJ/pixel of image task, which offers a scalable and energy-efficient solution for versatile IoT deployments.

The growing demand for high-performance components in wireless communication and automotive systems, especially for radar applications, has driven the need for dual-band power amplifiers (PAs) operating at 60GHz and 77GHz. These frequency bands are particularly beneficial for automotive radar systems, integral to Advanced Driver Assistance Systems (ADAS) and autonomous driving technologies, as they offer enhanced resolution, reduced interference, and faster data transmission rates. This paper presents the design and development of a dual-band PA based on a novel coupled-line dual-frequency matching structure. The PA’s innovative input and output matching networks utilize a unique coupler design to achieve simultaneous impedance matching at both 60GHz and 77GHz. Through comprehensive simulation, optimal matching impedances for both frequencies were identified, enabling the PA to achieve an output power of 12 dBm at 60GHz and 10 dBm at 77GHz, with power-added efficiencies of 24.4% and 13.85%, respectively. The design also incorporates a two-stage power amplifier configuration that ensures high efficiency and gain across the dual bands. Experimental validation was performed using a small-signal test system, demonstrating excellent performance, with a peak power gain of 12.4 dB at 60GHz and 9.8 dB at 77GHz. This dual-band PA design is particularly well-suited for integration into automotive radar systems, thanks to its compact size, high power efficiency, and ability to support wideband matching. Furthermore, this work presents a highly efficient, wideband solution for next-generation automotive radar and communication systems operating in the millimeter-wave frequency range.

This paper presents a PVT-robust, high gain range and high linearity analog baseband (ABB) circuit for wideband communication. The ABB circuit consists of a four-stage programmable gain amplifier (PGA) and an embedded second-order low pass filter (LPF). In order to satisfy the PVT variations, a novel PGA topology based on two-stage miller OTA with self PVT compensation and dynamic pole-capturing technique is proposed. Besides, the ABB circuit uses floating-bulk bias method to achieve high linearity. Fabricated in 28-nm CMOS process, the measurement results show that the ABB circuit can provide a programmable gain range from 0 to 40 dB with 6 dB coarse and 1 dB fine step, while the 3 dB bandwidth greater than 550 MHz. It obtains an OP1dBof 5dBm and OIP3 of 26.1dBm for the maximum gain state. The ABB circuit occupies a core area of 0.23 mm2and consumes a DC power consumption of 15 mW from 0.9-V supply.

This paper presents a cryogenic qubit controller for scalable superconducting quantum computing. A phase-selection digital power amplifier (DPA) topology is utilized for the XY-driving pulses generation. With a compact digital extensive architecture, the amplitude modulation and qubit phase rotation can be directly implemented at the phase-selection DPA stage for power reduction. A multi-phase envelope-tracking supply unit is also employed to enhance the power efficiency. The controller was designed and simulated in 28nm bulk CMOS technology. The controller can cover a band of 4-6GHz with an output power of at least -8dBm. The simulated SNR/SFDR is better than 55dB/46dB with a phase rotation error of less than 0.7°. The envelope-tracking supply unit can reduce the DPA power consumption by at least 24% compared to a constant power supply. The total power consumption of the controller is 3.64mW.

The timely detection of partial discharge (PD) of high-voltage (HV) power equipment is crucial to mitigate serious consequences such as the degradation of insulation and equipment failure. The ultra-high frequency (UHF) detection method stands out for its efficacy in this regard. In this study, a novel UHF antenna sensor is proposed for PD detection. The antenna's offset structure enables it to detect PD events near a conducting ground wire without being clamped to the wire like the typical high-frequency current transformer (HFCT). Meanwhile, its equivalent circuit is modeled as a ladder-structure band-pass filter (within the consideration of mutual inductances) to realize its wideband properties. Fabricated on a substrate and integrated with a low-noise amplifier, the antenna sensor exhibits a broad impedance bandwidth between 1 MHz and 108 MHz, as demonstrated through measurements in an anechoic chamber. In-lab and on-site systematic experiments affirm the efficiency of the proposed antenna sensor in PD detection. Notably, the Phase-Resolved Partial Discharge (PRPD) pattern is distinctly observable at the backend through Internet connectivity, further confirming the overall monitoring capabilities.

A Q-learning based current-steering digital to analog converter (DAC) calibration method is proposed in this paper for spurious-free dynamic range (SFDR) improvement. A look-up table (LUT) to control the switching sequence of the DAC elements is achieved by Q-learning for an optimal SFDR. Compared with the fixed element transition strategy proposed by manual derivation, the LUT can be updated by off-line training to deal with diverse and complex non-ideal factors limiting the SFDR of DAC. In this paper, a 2.0-GS/s 12-bit segmented current-steering DAC in 28nm process is simulated and the equivalent model is extracted to verify the effectiveness of the method. Simulation results show that, the SFDR over entire Nyquist bandwidth is larger than 70 dB with about 8 dB improvement using the proposed Q-learning method.

With the rapid development of the techniques of semiconductors, Internet of Everything (IoE), industry 4.0 and smart power are going to be realized, agile and accurate edge detection on pulse signals becomes essential for supporting versatile sensing applications targeting ubiquitous IoE monitoring. To ensure accurate pulse signal sensing at the edge with low power, a novel silicon-integrated mixer-enabled adaptive sensing platform is proposed. Based on the innovative chip architecture composed of the low-power ring voltage-controlled oscillator (VCO) and current-bleeding mixer on-chip, the wideband pulse signal would be mixed with the sinusoidal LO signal generated by VCO and detected by low-pass filtering and further digital processing. The frequency of the VCO can be configured flexibly by the FPGA to cover different pulse detection scenarios. Moreover, the VGA and the LPF are flexibly configurable to meet the link budget requirements and ensure accurate and adaptable detection covering various scenarios. Based on the systematic theoretical evaluation of the novel flexible sensing chip architecture, target pulse signals can be detected, exploring the capability of the efficient chip-based edge pulse detection system to be deployed for applications such as sustainable partial discharge detection for power electronics monitoring, ultrasound sensing, and so on.

This paper presents a 915MHz band ultra-low-power receiver with high energy efficiency for IoT applications. With the proposed polar receiver topology, the received Star- 16QAM signal is split into an ASK signal and D8PSK signal. A phase-tracking loop working as a phase domain ADC is adopted to demodulate the D8PSK signal, while the ASK signal can be demodulated by using a mixer-based energy detector chain. The receiver was designed and simulated in 65nm CMOS technology. Under 1V supply voltage, the power consumption of 445 μ W and the energy efficiency of 110pJ/bit have been achieved, which is at least 3.5× and 7.1 × better than prior arts, respectively. The simulated sensitivity is -76dBm at a data rate of 4Mbps. The figure of merit (FoM) of the receiver is 176dB.

Motivated by the ultra-low power design demands of the integrated implantable medical electronics and systems, a switched-capacitor DC-DC converter is presented in this paper. The DC-DC converter is controlled by hysteretic control approach, which has inherently stable and fast loop speed compared with the approach using error amplifier. To achieve higher power efficiency and lower quiscent current, in addition to optimizing the switching frequency and width of the core module of the converter, Low power design methodes are used for the functional module. By operating transistors in the subthreshold region and decreasing operating frequency, the short current and dynamic power can reduce a lot. The converter has designed in 0.18μm standard CMOS technology. It can achieve step down voltage conversion of 1.2V with a ripple voltage of 1.4mV from 2.5V input voltage. A high power efficiency of 88.3% can be achieved at a load current of 3μA. It also produces about 34nA low quiescent current without load, which is suitable for the integrated implantable biomedical electronics.

Impedance matching plays an important role in radio frequency circuits. To achieve dynamic load modulation in back-off operation for power amplifier or address the variation of antenna impedance due to complicated environment, tunable matching networks are demanded. To optimally design the coverage area within the Smith Chart for common ladder networks, analytic calculating procedure and computer optimization method has been proposed. The calculating procedure can be applied to arbitrary ladder networks and the optimization algorithm can acquire the optimal network automatically with appropriate constraints.

This paper presents a fully-integrated 8 MHz relaxation oscillator for ultra-low-power applications. Fabricated in 0.13 μm CMOS process, the oscillator occupies an area of 0.022 mm2. With adaptive reference generation and low-swing oscillation design, the power consumption is 2.8 μW, resulting a figure-of-merit of 0.35 nW/kHz. The adaptive reference feedback compensates the comparator delay and filters out the low-offset frequency part of the noise and temperature variation. To reduce the frequency influence due to current mismatch on the reference voltage and oscillation node, cascode current mirrors are applied. To reduce the influence due to the delay of capacitor reset logic, a pulse-to-edge generation block is used. The measured temperature stability is 1.24% in the temperature range of -20 °C to 60 °C and the measured periodic rms jitter is 180 ps, 0.144 % jitter-per-period on the output.

A 4-bit 4Msps successive approximation (SAR) phase-domain analog-to-digital converter (Ph-ADC) for zero intermediate frequency (IF) Bluetooth low energy (BLE) receivers is proposed. With the SAR operation, the Ph-ADC requires only 52 current elements and 1 comparator, in contrast to the conventional design which needs 260 current elements and 8 comparators. Simulation results show that the digital intensive Ph-ADC consumes only 7.9μA current from a 1.8V supply when implemented in a 180nm CMOS process.

An energy-efficiency 16-QAM/MSK transmitter (TX) working at 432 MHz is presented for the short range communications. By adopting the edge-combining power amplifier (ECPA), only an injection-locked ringing oscillator (ILRO) with very low frequency is required, in comparison to the high frequency local oscillator in conventional TX's, which helps to reduce the power consumption of this TX significantly. A new method to control the amplitude of the edge-combined quadrature signals is proposed to generate the 16-quadrature amplitude modulation (16-QAM) and minimum shift keying (MSK) modulations in this work. A finite impulse response (FIR) filter is introduced in the ECPA for side lobe suppression enhancement. Implemented in a 0.18 μm CMOS process, the proposed TX consumes 468 μW when outputting -15 dBm 50 Mbps 16-QAM/MSK signals in simulation. Under 1 V supply, the TX can achieve an energy efficiency of 9.4 pJ/bit at the maximum data rate of 50 Mbps. The phase noise of the RF output in the injection-locked state is -103 dBc/Hz, at 1MHz offset.