Co-packaging microfluidics and integrated circuits (ICs) has allowed for increasingly integrated lab-on-chip and lab-on-CMOS systems. Many of these, however, still required external hardware for pumping. Here, a combination of wafer-level molding and 3D-printing is used to package an IC with thermal inkjet (TIJ) capabilities as a micropump, coupled with package-level microfluidics and electrodes for impedance sensing. Including TIJ dispense capability in the package eliminates the need for external pumps for delivering fluid to the sensor. The TIJ IC acts as a pull-pump, ejecting waste solution and pulling new solution from an input port across a set of gold electrodes on the package surface. These electrodes are situated on the floor of a microfluidic channel and can be used to measure impedance, such as for electrical cell counting, and also to electrically estimate volumetric flow rate from transient signals, given known electrode spacing. To demonstrate, impedance measurements of 4.5 μm poly beads were performed at droplet ejection rates ranging from 63-200 Hz, and an estimated flow rate of 1.77 nl/min/Hz is shown using both electrical and optical tracking methods. Long-term, this approach can provide integrated pumping for multi-chip lab-on-CMOS systems in overmolded substrates.

High-resolution Discrete-Time ADCs are challenging to drive due to their large input sampling capacitance for thermal noise suppression. Predictive level-shifting, an integrated input driving technique for high-resolution ADCs, enables rail-to-rail linear operation of the input buffer without requiring a higher supply voltage. Using this technique, a predictor implemented as an active analog differentiator is used to preset an analog level shifter so that the input signal is shifted toward the smaller range. In this paper, a digital predictor based on a finite impulse response (FIR) filter is explored to overcome the limitations of the analog predictor, such as process, voltage and temperature (PVT) variations and device saturation. The digital predictor saves 48% power and produces 58% less prediction error compared to its analog counterpart, resulting in a more power-efficient ADC system.

Strain sensors are critical for wearable electronics and soft robotics applications, where knowledge of mechanical stress and linear stretch are essential. In this work, we present a multi-segment strain sensor using liquid metal paste to create a single pair of conductors in a stretchable substrate made of silicone. The sensor is designed as a piecewise transmission line, where each segment has a different characteristic impedance. We use a time domain reflectometry measurement method as an alternative to typical resistive or capacitive strain sensors. The length of each segment is determined by introducing a voltage pulse at one end of the sensor and measuring the round-trip time-of-flight of resulting reflected voltages caused by the discrete impedance discontinuities. Active electronics are only needed at one end of the sensor. In addition, it is linear and highly stretchable. Here we present the theory behind the measurement technique, brief sensor fabrication methods, and measured results from tested 3-segment and 5-segment strain sensors. Long-term, this approach may enhance strain sensor readout for wearable electronics, including biomechanical measurements and gesture recognition, as well as incorporation into soft robotic systems.

Traditional neurosensor arrays are constructed from passive metal electrodes that require one read-out wire for each sensor. The space required for wiring has become a critical bottleneck to increasing sensor count. It has been demonstrated that an array of active graphene sensors can be operated using less than one wire per sensor by using amplitude-modulation and frequency-division multiplexing (FDM), but results have been limited to measuring sub-kilohertz neural oscillations. In this work, we demonstrate an active graphene field effect transistor (GFET) electrode and FDM approach that can record spiking patterns with frequency components in the kilohertz band as required for single-neuron recordings, and combined sensor outputs on a single shared wire. Measured results include kilohertz signal bandwidth recovered from modulation frequencies up to 90 kHz, negligible cross-talk between signals transmitted on a shared output wire, and experiments showing that liquid-gated active graphene sensors can be operated with carrier frequencies up to 1 MHz. Long-term, megahertz carrier frequencies promise sufficient frequency-domain spacing to multiplex dozens of kilohertz neural signals on each shared output wire.

Biopotential signal acquisition for ECG, EEG, and other ExG monitoring applications is tending toward higher electrode count to provide increased resolution and accuracy. In turn, increasingly large wire bundles limit both scalability and ambulatory use. Frequency-division multiplexing (FDM) architectures have been employed to decrease wire count, where channel count is limited by modulation harmonics. In this work, we present an FDM-based active electrode architecture that uses harmonic cancellation to extend the available modulation frequency bandwidth by 3X compared to recent state-of-the art FDM-based biopotential readout systems, while maintaining similarly low power operation. Measured results from a 0.18$\mu \mathbf{m}$CMOS prototype IC demonstrate single- and multi-channel operation, with each active electrode circuit consuming only$\mathbf{12}\mu \mathbf{W}$and 0.3 mm2per channel. In addition, fully digital demodulation enables one-wire operation between multiple active electrodes and a back-end readout system. This approach addresses a fundamental challenge for future scalability applied to many-electrode bioelectrical measurement systems.

A highly reconfigurable gamma spectrometer with a silicon photomultiplier detector and a custom integrated circuit (IC)-based multi-channel analyzer (MCA) is presented. The core of the MCA comprises a custom analog front-end IC and a piecewise-linear analog-to-digital converter (ADC) IC, both fabricated in a 180nm complementary metal-oxide-semiconductor (CMOS) process. Along with a field-programmable gate array (FPGA)-based digital back-end, the proposed architecture allows pulse-height analysis with reconfigurable analog gain and ADC resolution across the full dynamic range. Specifically, the piecewise-linear ADC can increase resolution in selected regions of interest while utilizing a fixed 7-bit digital word, thus enabling data reduction and spectrum feature enhancement. Reconfigurability also allows the MCA to be tuned for different scintillator materials used in the detector. The system architecture is introduced at a conceptual level, followed by detector and circuit-level MCA implementation details and design trade-offs. Several isotope spectra were recorded with two common scintillators, LYSO and CsI(Tl), spanning energy peaks from 32keV to 1.33MeV. Variable energy bin-widths were measured across different AFE gains, ranging from 3keV to 58keV for LYSO, and 1.4keV to 51keV for CsI(Tl), demonstrating the versatility of the proposed system and its ability to provide reconfigurable peak enhancement for radiation spectroscopy.

Studies have shown that picking techniques play an important role in determining fruit quality at harvest (e.g. bruising, stem retention, etc). When picking fruit such as apples and pears, professional pickers use active perception, incorporating both visual and tactile input about fruit orientation, stem location, and the fruit’s immediate surroundings. This combination of tactile, visual, and force feedback is what enables human workers to execute dynamic movements that quickly and efficiently remove fruit from the tree without damage. However, much of the prior work on robotic fruit picking has formulated the harvesting problem as a position-control problem, using visual feedback for closed-loop end-effector placement while disregarding feedback on physical contact. As a first step towards more intelligent fruit picking — combining proprioception, localized sensing, and observed forces — we have developed a custom end-effector with multiple in-hand sensors, including tactile sensors on the fingertips. This paper presents the mechatronic design of the device as well as results from multiple outdoor picking trials with a Honeycrisp apple tree. Preliminary results show that, with multi-modal sensing, fruit slip, fruit separation from the tree, and fruit release from the hand can be detected.

A 0-2 Multi Stage Noise Shaping (MASH) analog-to-digital converter (ADC) is proposed. A SAR ADC and a VCO-based quantizer (VCOQ) are used in the first stage and second stages, respectively. The VCOQ proposed in this paper achieves second-order noise shaping by employing an error feedback architecture. The error feedback architecture is implemented by extracting the quantization noise of the VCOQ as a pulse-width-modulated (PWM) signal, and feeding it back to the VCO input using a charge pump. The proposed architecture filters the charge pump errors. Also, SAR comparator thermal noise requirement is relaxed as the comparator noise is canceled at the output, along with the first stage quantization noise. The proposed ADC was simulated using a 65nm CMOS technology, and an SNDR of 89.5 dB was achieved with an oversampling ratio (OSR) of 20.

Energy harvesting from ambient sources, such as body temperature, is an attractive solution for powering battery-less wearable electronics used for healthcare diagnostics. While feasible from an energy standpoint, initial start-up of an energy harvesting circuit from a millivolt-level thermoelectric generator output poses a particular challenge. One approach to boosting such a low input voltage is to use a low-voltage oscillator to start up a higher voltage DC-DC converter. In this work, we demonstrate a modified ring-oscillator architecture using a stacked three-inverter delay element, which can generate self-sustained oscillation from an input supply voltage as low as 50 mV. Compared to inductor-based on-chip oscillators or those using native transistors, this architecture significantly reduces circuit area and expands process compatibility. The start-up oscillator is implemented in a standard 0.18 μm CMOS process and comprises 21 stages; it generates a clock of frequency 9.5 kHz with a 86% voltage swing from an input supply voltage of 50 mV, while occupying less than 0.003 mm2and consuming 818 pW.

Switched-capacitor charge pumps provide fully-integrated voltage conversion in integrated circuits, without the need for large area inductors. Traditional cross-coupled charge pump topologies are limited by reversion loss, where charge flows backward during a pumping cycle due to non-ideal switch control clocks. In this work, we present two modified charge pump topologies that eliminate reversion loss while adding minimal control complexity. A detailed comparison with recent published approaches is presented. The single-stage charge pump Designs I and II are implemented in a standard 180 nm CMOS process and exhibit peak efficiency of 81.9% and 83.2%, respectively, and more than 70% power efficiency is achieved across a load current range from 100-900 μA for Design II. The presented approach improves efficiency while decreasing required stage capacitance several-fold, achieving over 87 mW/mm2power density.

Single-photon avalanche diodes (SPAD) are high sensitivity photon detectors used in time-resolved imaging and very low-light applications. Operation as an avalanche detector requires reverse bias beyond the breakdown voltage, which is typically much higher than supported voltages in a standard CMOS process. In order to realize a fully integrated photon detection system using SPAD devices, this high-voltage bias needs to be generated on chip. Generated voltages beyond the breakdown threshold of the process pose particular design challenges, especially for output sampling and closed-loop regulation. This paper presents design and architectural techniques used to implement a closed-loop DC-DC converter that can be fully integrated on-chip and produces a regulated output voltage exceeding 15 V. Particular design constraints imposed by high on-chip voltages are addressed, and presented simulation results are based on an implemented design in a standard 130 nm CMOS process. The charge pump generates an output voltage of 15 V in 2 μs from start, with a modeled SPAD load of 10 pF. Following an avalanche current pulse, the recovery transient time is <;150 ns to settle within 140 mV of the desired output voltage.