This paper presents the application of a novel target tracking technique employing tensor decompositions for discretizing the target state space. The time evolution of the conditional probability density is realized by a Fokker-Planck equation solver and the measurement update, as usual, by applying Bayes’ rule. The method is applicable to non-Gaussian and non-linear system equations and enables the treatment of complex non-Gaussian target state densities. In addition, the efficient tensor decomposition scheme, in principle, allows for high-dimensional target states. The new tracking filter is applied to the problem of tracking an agile air target using bearing measurements from distributed acoustic and electromagnetic array sensors based on real data. It is shown that the new filter is able to initiate and maintain the target track with localization errors comparable to those of a standard particle filter.

To host intelligent algorithms such as Deep Neural Networks on embedded devices, it is beneficial to transform the data representation of neural networks into a fixed-point format with reduced bit-width. In this paper we present a novel quantization procedure for parameters and activations of pre-trained neural networks. For 8 bit linear quantization, our procedure achieves close to original network performance without retraining and consequently does not require labeled training data. Additionally, we evaluate our method for power-of-two quantization as well as for a two-hot quantization scheme, enabling shift-based inference. To underline the hardware benefits of a multiplierless accelerator, we propose the design of a shift-based processing element.

We present a Vector Processing Engine (VPE) designed for the acceleration of Convolutional Neural Networks (CNNs) for semantic segmentation. Most CNN accelerators focus on classification. However, CNNs for semantic segmentation incorporate special layer types. Our accelerator supports not only regular convolutional layers, but also dilated convolutions and convolutions in combination with down- or up-sampling. These features are implemented in dedicated address generators which load the corresponding input vector from an input line buffer. The VPE is designed as a 64x64-array where up to 64 output features and 64 input features of a convolutional layer can be unrolled in parallel. The array has a peak performance of 4.12 TOp/s and achieves 3.85 TOp/s on a CNN for semantic segmentation - resulting in an average utilization of 93 %. The design is prototypically implemented on a Virtex UltraScale+ device with a clock rate of 250 MHz. In addition to the overall architecture, we present the two-hot quantization scheme. A value in two-hot quantization can be regarded as a combination of two power-of-two values. Hence, instead of bulky multipliers, two small bit-shifts are implemented. We design and implement dedicated arithmetic engines for this quantization scheme. Additionally, we evaluate this quantization scheme on the rather complex task of semantic segmentation. We show that the performance of an 8 bit two-hot quantization scheme is marginally lower in comparison to a regular 8 bit fixed-point variant.

Machine Learning techniques such as Support Vector Machines (SVM) have found applications in many fields, e.g. in Wireless Sensor Networks (WSN) and sensor data processing in general. Especially in the case of WSN energy is very limited as agents solely operate based on battery power after they have been deployed, therefore energy efficiency is of great importance. Furthermore, agents are supposed to adapt to their environment by being capable of re-training themselves based on feedback they get from their surroundings, which increases the computational demands on the digital hardware involved. To meet these demands, dedicated hardware in form of a very-large-scale integrated (VLSI) circuit is a reasonable approach and is investigated here. In this paper a specific variant of the SVM — the Least-Squares SVM — is implemented as VLSI circuit. Additionally during the training phase a subset-selection technique based on the quadratic Renyi entropy is implemented in order to reduce the computational and hardware demands. The resulting design consumes 21.35 mW and requires an area of 81.2 kGE without memories.