Integrating machine learning (ML) models directly in the network user plane enables inference on data traffic at line rate, and can dramatically reduce the latency and improve the scalability of key functionalities like traffic classification or intrusion detection. Yet, the hardware that can be used for this purpose, in particular programmable switches, present stringent constraints in terms of limited memory and little support for mathematical operations or data types that render ML model deployment a substantial technical challenge. In this paper, we make a step forward in user-plane ML by introducingFlowrest, a solution that redefines the state of the art in flow-level inference for programmable switches.Flowrestallows implementing general-purpose Random Forest (RF) models in industry-grade switches by ($\boldsymbol {i}$) suitably handling stateful flow-level (FL) features in the switch ASIC, ($\boldsymbol {ii}$) achieving low-collision flow management, and ($\boldsymbol {iii}$) customizing RF models right from the design phase for in-switch operation. We developFlowrestas an open-source software using the P4 language and evaluate its performance in an experimental testbed with Intel Tofino switches. Experiments with inference tasks of varying complexity prove that our solution improves accuracy by over 10 percent points on average with respect to the second-best competitor out of five recent approaches for RF-based in-switch inference, while maintaining sub-microsecond latency.

Embedding machine learning (ML) models in programmable switches realizes the vision of high-throughput and low-latency inference at line rate. Recent works have made breakthroughs in embedding Random Forest (RF) models in switches for either packet-level inference or flow-level inference. The former relies on simple features from packet headers that are simple to implement but limit accuracy in challenging use cases; the latter exploits richer flow features to improve accuracy, but leaves early packets in each flow unclassified. We propose Jewel, an in-switch ML model based on a fully joint packet-and flow-level design, which takes the best of both worlds by classifying early flow packets individually and shifting to flow-level inference when possible. Our proposal involves (i) a single RF model trained to classify both packets and flows, and (ii) hardware-aware model selection and training techniques for resource footprint minimization. We implement Jewel in P4 and deploy it in a testbed with Intel Tofino switches, where we run extensive experiments with a variety of real-world use cases. Results reveal how our solution outperforms four state-of-the-art benchmarks, with accuracy gains in the 2.0%–5.3% range.

Recent endeavours have enabled the integration of trained machine learning models like Random Forests in resource-constrained programmable switches for line rate inference. In this work, we first show how packet-level information can be used to classify individual packets in production-level hardware with very low latency. We then demonstrate how the newly proposed Flowrest framework improves classification performance relative to the packet-level approach by exploiting flow-level statistics to instead classify traffic flows entirely within the switch without considerably increasing latency. We conduct experiments using measurement data in a real-world testbed with an Intel Tofino switch and shed light on how Flowrest achieves an F1-score of 99% in a service classification use case, outperforming its packet-level counterpart by 8%.

In this paper we study the capability of LoRa technology in rejecting different interfering LoRa signals and the impact on the cell capacity. First, we analyze experimentally the link-level performance of LoRa and show that collisions between packets modulated with the same Spreading Factor (SF) usually lead to channel captures, while different spreading factors can indeed cause packet loss if the interference power is strong enough. Second, we model the effect of such findings to quantify the achievable capacity in a typical LoRa cell: we show that high SFs, generally seen as more robust, can be severely affected by inter-SF interference and that different criteria for deciding SF allocations within the cell may lead to significantly different results. Moreover, the use of power control and packet fragmentation can be detrimental more than beneficial in many deployment scenarios. Finally, we discuss the capacity improvements that can be achieved by increasing the density of LoRa gateways. Our results have important implications for the design of LoRa networks: for example, allocating high SFs to faraway end devices might not improve the experienced performance in case of congested networks because of the increased transmission time and vulnerability period.

In this demo we present and validate a LoRa cell traffic generator, able to emulate the behavior of thousands of low-rate sensor nodes deployed in the same cell, by using a single Software Defined Radio (SDR) platform. Differently from traditional generators, whose goal is creating packet flows which emulate specific applications and protocols, our focus is generating a combined radio signal, as seen by a gateway, given by the super-position of the signals transmitted by multiple sensors simultaneously active on the same channel. We argue that such a generator can be of interest for testing different network planning solutions for LoRa networks.