Marc Zyngier

dblp:207/1852 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2017
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Cloud and datacenter computing · 70% Processor architecture and microarchitecture · 30%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture › instruction set architecture › RISC
ARM architecture
0.312017
NEVE: Nested Virtualization Extensions for ARM · SOSP 2017
Cloud and datacenter computing › virtualization
nested virtualization
0.312017
NEVE: Nested Virtualization Extensions for ARM · SOSP 2017
Cloud and datacenter computing
virtualization
0.312017
NEVE: Nested Virtualization Extensions for ARM · SOSP 2017
Cloud and datacenter computing › virtualization
virtual machine monitor
0.112017
NEVE: Nested Virtualization Extensions for ARM · SOSP 2017

Methods — techniques the papers use, named apart from their topics

paravirtualization · 0.3
YearPublicationVenuePosition
2017 NEVE: Nested Virtualization Extensions for ARM
abstract
Nested virtualization, the ability to run a virtual machine inside another virtual machine, is increasingly important because of the need to deploy virtual machines running software stacks on top of virtualized cloud infrastructure. As ARM servers make inroads in cloud infrastructure deployments, supporting nested virtualization on ARM is a key requirement, which has been met recently with the introduction of nested virtualization support to the ARM architecture. We build the first hypervisor to use ARM nested virtualization support and show that despite similarities between ARM and x86 nested virtualization support, performance on ARM is much worse than on x86. This is due to excessive traps to the hypervisor caused by differences in non-nested virtualization support. To address this problem, we introduce a novel paravirtualization technique to rapidly prototype architectural changes for virtualization and evaluate their performance impact using existing hardware. Using this technique, we propose Nested Virtualization Extensions for ARM (NEVE), a set of simple architectural changes to ARM that can be used by software to coalesce and defer traps by logging the results of hypervisor instructions until the results are actually needed by the hypervisor or virtual machines. We show that NEVE allows hypervisors running real application workloads to provide an order of magnitude better performance than current ARM nested virtualization support and up to three times less overhead than x86 nested virtualization. NEVE will be included in ARMv8.4, the next version of the ARM architecture.
Jin Tack Lim, Christoffer Dall, Shih-Wei Li, Jason Nieh, Marc Zyngier
SOSP5