VLDB 2026 Research / reviewers in the wild / expert
Gregoire Gimenez
dblp:207/3940 · also Grégoire Gimenez
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2018
0000-0002-5166-8903ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware reliability and fault tolerance · 87% Embedded and real-time systems · 13% |
Topics — the 2 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware reliability and fault tolerance › soft errors
soft error mitigation |
0.3 | 1 | 2018 | The Arm Triple Core Lock-Step (TCLS) Processor · ACM Trans. Comput. Syst. 2018 |
Embedded and real-time systems › critical systems
safety-critical systems |
0.1 | 1 | 2018 | The Arm Triple Core Lock-Step (TCLS) Processor · ACM Trans. Comput. Syst. 2018 |
Methods — techniques the papers use, named apart from their topics
rad-hard by design · 0.3commercial cell libraries · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2018 | The Arm Triple Core Lock-Step (TCLS) ProcessorabstractThe Arm Triple Core Lock-Step (TCLS) architecture is the natural evolution of Arm Cortex-R Dual Core Lock-Step (DCLS) processors to increase dependability, predictability, and availability in safety-critical and ultra-reliable applications. TCLS is simple, scalable, and easy to deploy in applications where Arm DCLS processors are widely used (e.g., automotive), as well as in new sectors where the presence of Arm technology is incipient (e.g., enterprise) or almost non-existent (e.g., space). Specifically in space, COTS Arm processors provide optimal power-to-performance, extensibility, evolvability, software availability, and ease of use, especially in comparison with the decades old rad-hard computing solutions that are still in use. This article discusses the fundamentals of an Arm Cortex-R5 based TCLS processor, providing key functioning and implementation details. The article shows that the TCLS architecture keeps the use of rad-hard technology to a minimum, namely, using rad-hard by design standard cell libraries only to protect the critical parts that account for less than 4% of the entire TCLS solution. Moreover, when exposure to radiation is relatively low, such as in terrestrial applications or even satellites operating in Low Earth Orbits (LEO), the system could be implemented entirely using commercial cell libraries, relying on the radiation mitigation methods implemented on the TCLS to cope with sporadic soft errors in its critical parts. The TCLS solution allows thus to significantly reduce chip manufacturing costs and keep pace with advances in low power consumption and high density integration by leveraging commercial semiconductor processes, while matching the reliability levels and improving availability that can be achieved using extremely expensive rad-hard semiconductor processes. Finally, the article describes a TRL4 proof-of-concept TCLS-based System-on-Chip (SoC) that has been prototyped and tested to power the computer on-board an Airbus Defence and Space telecom satellite. When compared to the currently used processor solution by Airbus, the TCLS-based SoC results in a more than 5× performance increase and cuts power consumption by more than half. Xabier Iturbe, Balaji Venu, Emre Ozer 0001, Jean-Luc Poupat, Gregoire Gimenez, Hans-Ulrich Zurek |
ACM Trans. Comput. Syst. | 5 |