Optimizing mixed-signal systems-on-chips (SoCs) is a challenging task, especially when they involve both analog building blocks and machine-learning (ML) algorithms which make the overall system performance hard to predict. This paper proposes a methodology for optimizing complex mixed-signal sensor systems, which consists of three steps: (1) modeling Pareto-optimal local performance of individual circuits, (2) building a macromodel of the mixed-signal system performance including local non-idealities, and (3) finding the optimal set of system-level parameters using numerical optimization. The methodology is applied to the use case of an electrocardiogram (ECG) sensor system with embedded arrhythmia classification, with the objective of minimizing the system power consumption while imposing constraints on inference accuracy. Different numerical optimization methods are compared to evaluate their respective performance on the minimization task: gradient-based, genetic, or bayesian optimization. The proposed methodology achieves the optimization in a reasonable execution time of 10 hours, which had not been previously demonstrated on such complex mixed-signal system. Among the different methods tested, bayesian optimization provides the best success rate of 97% and fastest convergence speed.

Wireless power transfer (WPT) is a possible alternative to batteries for supplying smart sensors. It is often described as “greener" because it avoids the use of batteries. However, this claim usually lacks the proper assessment of the environmental impacts of WPT and is particularly questionable given the poor efficiency of wirelessly transmitting power over a few meters of distance. In this paper, we design and thoroughly optimize a complete state-of-the-art WPT system and compare it to an equivalent battery-powered solution to assess whether it effectively represents an eco-friendly alternative. The proposed WPT system is a 2.45-GHz simultaneous wireless information and power transfer (SWIPT) system with beamforming and a high peak-to-average power ratio waveform for supplying a battery-less passive infrared sensor for room occupancy tracking. The final prototype of the smart sensor consumes 4and can operate in steady state at 5from the remote power head with an overall power transfer efficiency of 17/and can cold-start at 3.5. We carry out a life-cycle assessment (LCA) of the environmental impacts through four indicators, i.e., primary energy demand, global warming potential, terrestrial ecotoxicity, and freshwater consumption. Results show that for a 10-year lifetime, the WPT alternative has at least 5.5 to 10.3× higher environmental impacts than its battery-powered equivalent. This demonstrates the importance of LCA during the design of IoT smart sensors and shows that the use of meter-range 2.45¯/GHz SWIPT should be limited to applications where conventional battery-powered systems cannot be used.

In information and communication technologies (ICTs), innovation is intrinsically linked to empirical laws of exponential efficiency improvement such as Moore's law. By following these laws, the industry achieved an amazing relative decoupling between the improvement of key performance indicators (KPIs), such as the number of transistors, from physical resource usage such as silicon wafers. Concurrently, digital ICTs came from almost zero greenhouse gas emission (GHG) in the middle of the twentieth century to direct annual carbon footprint of approximately 1400 MT CO2e today. Given the fact that we have to strongly reduce global GHG emissions to limit global warming below 2°C, it is not clear if the simple follow-up of these trends can decrease the direct GHG emissions of the ICT sector on a trajectory compatible with Paris agreement. In this paper, we analyze the recent evolution of energy and carbon footprints from three ICT activity sub-sectors: semiconductor manufacturing, wireless Internet access and datacenter usage. By adopting a Kaya-like decomposition in technology affluence and efficiency factors, we find out that the KPI increase failed to reach an absolute decoupling with respect to total energy consumption because the technology affluence increases more than the efficiency. The same conclusion holds for GHG emissions except for datacenters, where recent investment in renewable energy sources lead to an absolute GHG reduction over the last years, despite a moderate energy increase. We formulate hypotheses for this absence of absolute decoupling from three scientific fields: ecological economics, economics of technology and sociology of technology. We argue that aligning direct GHG emissions of the ICT sector on a trajectory compatible with Paris agreement requires an ecological transition in innovation by adopting sobriety in addition to efficiency.

In this paper, we propose a low-overhead solution to ensure contention-free data retention in clock-gated true single-phase-clock (TSPC) flip-flops (FF) at ultra-low voltage (ULV). It relies on a retention feedback loop added to the TSPC FF and controlled by the clock-gating module. When the clock is gated, the retention is enabled, which drives the FF in retention mode. This limits the energy overhead induced by the added feedback loop and makes the FF contention-free. Moreover, as several FFs typically share the same clock-gating module, the control signal generation overhead is also kept low. The proposed 19T TSPC FF with retention mode was implemented as a standard cell in 65nm LP CMOS. The FF energy is 0.5fJ/cycle at 0.4V, from post-layout simulations and for a typical 25% activity factor, which is 62% reduction compared to the conventional 24T master-slave FF. Experimental validation of a prototyped Cortex-M0 testchip including the integration of the proposed FF into synthesis and place/route flow validates its robust operation at ULV.