The growing demand for 3D modeling, particularly in applications like augmented reality (AR) and virtual reality (VR), has underscored the need for more efficient techniques. Manual 3D modeling requires extensive effort and a specialized skill set. Although traditional Photogrammetry is faster than manual 3D modeling, it is still compute-intensive and time-consuming. Emerging methods like 3D Gaussian Splatting (3DGS) offer a faster and more cost-effective solution for model generation (training), at the cost of requiring a different rendering framework. For their widespread adoption in applications such as AR and VR, it is crucial to meet rendering performance requirements, such as power and frame rate. Existing works mainly focus on 3DGS training performance and lack comprehensive analysis and comparison with traditional graphics (TG) rendering techniques that use a mesh representation. Hence, a thorough benchmarking of 3DGS rendering is necessary to identify its limitations and potential areas for improvement. In this paper, we conduct a comprehensive performance study of 3DGS rendering using state-of-the-art frameworks on three different hardware platforms. We evaluate 3DGS performance against TG rendering in terms of frames-per-second (FPS), power, GPU memory footprint, GPU utilization, frametime breakdown, FPS to Watt, several GPU performance counters, and rendered image quality. We observe that 3DGS generates high-quality images with an average PSNR of 37. Our analysis reveals that 3DGS rendering requires a 3x improvement in the FPS to Watt to achieve the performance of TG rendering. Our evaluation shows that 3DGS occupies, on average, a 2x lesser GPU memory footprint compared to TG rendering. Our results indicate that around 10 % image quality can be a tradeoff for a 100 % improvement in frame rate. We see that the rasterization step, on average, consumes 64.76 % of frame time and is the main bottleneck to 3DGS. We identify that 3DGS has, on average, 25 % higher GPU utilization than TG rendering. However, its performance is limited by stalls due to branching and synchronization, pointing to possible improvements in 3DGS algorithm and making it GPU friendly.

3D Gaussian Splatting (3DGS) combines classic image-based rendering, point-based graphics, and modern differentiable techniques, and offers an interesting alternative to traditional physically-based rendering. 3DGS-family models are far from efficient for power-constrained Extended Reality (XR) devices, which need to operate at a Watt-level. This paper introduces PowerGS, the first framework to jointly minimize the rendering and display power in 3DGS under a quality constraint. We present a general problem formulation and show that solving the problem amounts to 1) identifying the iso-quality curve(s) in the landscape subtended by the display and rendering power and 2) identifying the power-minimal point on a given curve, which has a closed-form solution given a proper parameterization of the curves. PowerGS also readily supports foveated rendering for further power savings. Extensive experiments and user studies show that PowerGS achieves up to 86% total power reduction compared to state-of-the-art 3DGS models, with minimal loss in both subjective and objective quality. Code is available at https://github.com/horizon-research/PowerGS.

Abstract We introduce Arches, a hardware simulation framework designed to explore and evaluate massively parallel ray‐tracing architectures. Operating at the cycle level, Arches captures detailed performance metrics, including computational throughput, on‐chip data movement across processors, caches, and off‐chip communication via an accurate memory system model. The framework is modular, allowing flexible configuration and interconnection of processor cores, caches, and custom hardware units, enabling easy exploration of diverse hardware architectures. Arches supports high‐performance parallel execution, simulating complex ray tracing workloads to image completion. It leverages the GNU toolchain, allowing users to write C++ software targeting both the simulated architecture and native execution for debugging, including support for custom instructions to control specialized hardware components. The framework provides comprehensive performance instrumentation, offering insights into time‐varying statistics across all modules and identifying performance bottlenecks. Our evaluations demonstrate that Arches delivers performance estimates closely matching real hardware, offering faster and more accurate simulations than existing open‐source hardware simulators. Its modularity also makes it a valuable tool for exploring alternative parallel computing strategies for high‐performance ray tracing, and its extensibility enables adaptation for other workloads or general‐purpose computation.

Abstract 3D Gaussian splatting (3DGS) has shown potential for rendering photorealistic 3D scenes in real‐time. Unfortunately, rendering these scenes on less powerful hardware is still a challenge, especially with high‐resolution displays. We introduce a continuous level of detail (CLOD) algorithm and demonstrate how our method can improve performance while preserving as much quality as possible. Our approach learns to order splats based on importance and optimize them such that a representative and realistic scene can be rendered for an arbitrary splat count. Our method does not require any additional memory or rendering overhead and works with existing 3DGS renderers. We also demonstrate the flexibility of our CLOD method by extending it with distance‐based LOD selection, foveated rendering, and budget‐based rendering.

We introduce a gaze-tracking-free method to reduce OLED display power consumption in VR with minimal perceptual impact. This technique exploits the time course of chromatic adaptation, the human visual system's ability to maintain stable color perception under changing illumination. To that end, we propose a novel psychophysical paradigm that models how human adaptation state changes with the scene illuminant. We exploit this model to compute an optimal illuminant shift trajectory, controlling the rate and extent of illumination change, to reduce display power under a given perceptual loss budget. Our technique significantly improves the perceptual quality over prior work that applies illumination shifts instantaneously. Our technique can also be combined with prior work on luminance dimming to reduce display power by 31% with no statistical loss of perceptual quality.

Real-time scene provisioning-reconstructing and delivering scene data to requesting XR applications during runtime-is central to enabling spatial computing in modern XR systems. However, existing solutions struggle to balance latency, power and scene fidelity under XR device constraints, and often rely on designs that are either closed, application-specific designs, or both. We present Ada, the first open distributed, power-aware, application-agnostic real-time scene provisioning system. Through computation offloading along with algorithmic and system innovations, Ada provides high-fidelity scenes with stable performance across all evaluated scene sizes and with low power consumption. To isolate the benefits of Ada's algorithmic and design innovations over the closest prior work [82], which is on-device and CPU-based, we configure a comparable on-device, CPU-based variant of Ada (AdaLocal-CPU). We show this variant achieves up to 6.8× lower scene request latency and higher scene fidelity compared to the prior work. Furthermore, Ada's final distributed GPU-accelerated implementation reduces latency by an additional 2×, highlighting the benefits of GPU acceleration and distributed computing. Additionally, Ada also lowers the incremental power cost of scene provisioning by 24% compared to the best on-device variant (AdaLocal-GPU). Finally, Ada flexibly adapts to diverse latency, power, scene fidelity, and network bandwidth requirements.

Chip manufacturers are constantly trying to increase the on-chip compute power to meet the ever increasing compute demands of modern computer applications. Such high compute power processor architectures often require a steady supply of large amounts of data to be able to make full use of their raw compute power. Historically, memory technologies have lagged behind the processors in terms of speed. So, memory bandwidth often becomes a performance limiter. Higher memory bandwidth also leads to an increase in the overall energy and power consumption of the system. As a result, reducing off-chip data traffic continues to be an important design problem for future processor architectures. In this paper, we identify a portion of off-chip traffic produced by modern graphics applications that can be avoided while maintaining functional correctness. We note that modern graphics applications produce a lot of intermediate data and that this intermediate data serves no purpose or becomes irrelevant after the application has consumed it. We show that a significant portion of the off-chip traffic is produced by this irrelevant intermediate data. We also propose a mechanism with which this off-chip traffic could be significantly reduced.

Single-thread performance improvement remains a central design goal for general purpose processors. Microarchitectural designs for the core have reached a plateau over the past years. However, we are still far from exhausting the implicit parallelism available in today's programs. One approach is to use a separate thread context to improve data and instruction supply to the main pipeline. Such decoupled look-ahead (DLA) architectures have been shown to be an effective way to improve single-thread performance. However, a default implementation requires an additional core. While an SMT flavor is possible, a naive implementation is inefficient and thus slow. In this paper, we propose an optimized implementation called Bootstrapping that makes DLA just as effective on a single (SMT) core as using two cores. While fusing two cores can improve single-thread performance by 1.22x, Bootstrapping provides a speedup of 1.48 over a broad range of benchmark suites, making it a compelling microarchitectural feature for general-purpose microarchitectures.

Modern societies have developed insatiable demands for more computation capabilities. Exploiting implicit parallelism to provide automatic performance improvement remains a central goal in engineering future general-purpose computing systems. One approach is to use a separate thread context to perform continuous look-ahead to improve the data and instruction supply to the main pipeline. Such a decoupled look-ahead (DLA) architecture can be quite effective in accelerating a broad range of applications in a relatively straightforward implementation. It also has broad design flexibility as the look-ahead agent need not be concerned with correctness constraints. In this paper, we explore a number of optimizations that make the look-ahead agent more efficient and yet extract more utility from it. With these optimizations, a DLA architecture can achieve an average speedup of 1.4 over a state-of-the-art microarchitecture for a broad set of benchmark suites, making it a powerful tool to enhance single-thread performance.

Prefetching is a central component in most microarchitectures. Many different algorithms have been proposed with varying degrees of complexity and effectiveness. There are inherent tradeoffs among various metrics especially when we try to exploit both simpler access patterns and more complex ones simultaneously. Hypothetically, therefore, it is better to have collaboration of sub-components each specialized in exploiting a different access pattern than to have a monolithic design trying to have a similar prefetching scope. In this paper, we present some empirical evidence. We use a few components dedicated for some simple patterns such as canonical strided accesses. We show that a composite prefetcher with these components can significantly out perform state-of-the-art prefetchers. But more importantly, the composite prefetcher achieves better performance through a more limited prefetching scope while attaining a much higher accuracy. This suggests that the design can be more readily expanded with additional components targeting other patterns.

Single-thread performance and throughput often pose different design constraints and require compromises. Mainstream CPUs today incorporate a non-trivial number of cores, even for mobile devices. For power and thermal considerations, by default, a single core does not operate at the maximum performance level. When operating conditions allow, however, commercial products often rely on turbo boosting, which temporarily increases the clock frequency to increase single-thread performance. However, increasing clock speed may result in a poor performance return for invested energy. In this article, we make a case for a more effective boosting strategy, which invests energy in activities with the best estimated return. In addition to running faster clocks, we can also use a look-ahead thread to overlap the penalties of cache misses and branch mispredicts. Overall, for similar power consumptions, the proposed adaptive turbo boosting strategy can achieve about twice the performance benefits while halving the energy overhead.

Prefetching is a central element in most microarchitectures. Many different algorithms have been proposed with varying degrees of complexity and effectiveness. There is a tradeoff among various aspects of coverage, accuracy, and cost, especially when we try to exploit both simpler access patterns and more complex ones simultaneously. In this paper, we propose a design that only targets canonical strided access patterns, but does so with a very high accuracy. Compared to many other state-of-the-art prefetchers, sometimes with much more ambitious coverage, our design incurs much less memory traffic, reduces energy consumption, while still performs better on average.