Demo Data from VLDB 2026 / reviewers in the wild / expert
Suyoung Choi
dblp:21/10715
· DBLP profile ↗
3ranked-venue papers
1as first author
3since 2021 · last 2025
0000-0002-3116-1072ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 since 2021Artificial intelligence and machine learning · 1 · 1 since 2021Theory of computation · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Artificial intelligence
1 paper |
Legged, aerial and field robots · 61% Robot navigation and mapping · 30% Probabilistic and Bayesian machine learning · 9% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 100% | |
| Theoretical computer science
1 paper |
Combinatorics and discrete mathematics · 100% |
Topics — the 7 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Robotics › Legged, aerial and field robots
legged robots |
0.9 | 1 | 2025 | Legged Robot State Estimation with Invariant Extended Kalman Filter Using Neural Measurement Network · ICRA 2025 |
Robotics › Legged, aerial and field robots › legged robots
legged robot state estimation |
0.9 | 1 | 2025 | Legged Robot State Estimation with Invariant Extended Kalman Filter Using Neural Measurement Network · ICRA 2025 |
Robotics › Robot navigation and mapping
localization |
0.9 | 1 | 2025 | Legged Robot State Estimation with Invariant Extended Kalman Filter Using Neural Measurement Network · ICRA 2025 |
Combinatorics and discrete mathematics
polytope theory |
0.8 | 1 | 2024 | GPU Algorithm for Enumerating PL Spheres of Picard Number 4: Application to Toric Topology · SoCG 2024 |
Integrated circuit design › digital circuit design › sequential circuit design
counter design |
0.7 | 1 | 2023 | High-Speed Counter With Novel LFSR State Extension · IEEE Trans. Computers 2023 |
Integrated circuit design
digital circuit design |
0.7 | 1 | 2023 | High-Speed Counter With Novel LFSR State Extension · IEEE Trans. Computers 2023 |
Machine learning › Probabilistic and Bayesian machine learning › statistical inference › bayesian inference › bayesian filtering
kalman filtering |
0.3 | 1 | 2025 | Legged Robot State Estimation with Invariant Extended Kalman Filter Using Neural Measurement Network · ICRA 2025 |
Methods — techniques the papers use, named apart from their topics
sim-to-real transfer · 0.9neural measurement network · 0.9invariant extended kalman filter · 0.9simplicial isomorphism · 0.8matroid theory · 0.8
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Legged Robot State Estimation with Invariant Extended Kalman Filter Using Neural Measurement NetworkabstractThis paper introduces a novel proprioceptive state estimator for legged robots that combines model-based filters with deep neural networks. In environments where vision systems are not reliable, proprioceptive state estimators become indispensable. Traditionally, proprioceptive state estimators are based on model-based approaches, which rely solely on contact foot kinematics as measurements. In contrast, learning-based approaches have obtained new measurements, such as displacement and covariance, by leveraging real-world data in a supervised manner. In this work, we develop a state estimation framework that trains a neural measurement network (NMN) to estimate the base's linear velocity and foot contact probability, which are then employed as measurements in an invariant extended Kalman filter. Our approach relies solely on simulation data for training, as it allows us to obtain extensive data easily. We address the sim-to-real gap by adapting existing learning techniques and regularization. To validate our proposed method, we conduct hardware experiments using a quadruped robot on four types of terrain: flat, debris, soft, and slippery. In our experiments, the proposed method demonstrates significant improvements over the model-based state estimator, achieving an average reduction in Absolute Trajectory Error (ATE) by${6 1. 8 \%}$for position and${8. 5 \%}$for velocity. Donghoon Youm, Hyunsik Oh, Suyoung Choi, Hyeongjun Kim, Seunghun Jeon, Jemin Hwangbo |
ICRA | 3 |
| 2024 | GPU Algorithm for Enumerating PL Spheres of Picard Number 4: Application to Toric TopologyabstractThe fundamental theorem for toric geometry states a toric manifold is encoded by a complete non-singular fan, whose combinatorial structure is the one of a PL sphere together with the set of generators of its rays. The wedge operation on a PL sphere increases its dimension without changing its Picard number. The seeds are the PL spheres that are not wedges. A PL sphere is toric colorable if it comes from a complete rational fan. A result of Choi and Park tells us that the set of toric seeds with a fixed Picard number p is finite. In fact, a toric PL sphere needs its facets to be bases of some binary matroids of corank p with neither coloops, nor cocircuits of size 2. We present and use a GPU-friendly and computationally efficient algorithm to enumerate this set of seeds, up to simplicial isomorphism. Explicitly, it allows us to obtain this set of seeds for Picard number 4 which is of main importance in toric topology for the characterization of toric manifolds with small Picard number. This follows the work of Kleinschmidt (1988) and Batyrev (1991) who fully classified toric manifolds with Picard number ≤ 3. Suyoung Choi, Hyeontae Jang, Mathieu Vallée 0002 |
SoCG | 1 |
| 2023 | High-Speed Counter With Novel LFSR State ExtensionabstractThis paper presents a high-speed counter architecture associated with novel LFSR state extension. By employing the proposed state extension, an$\emph {m}$-bit LFSR counter with$(\mathrm{2^{\mathit{m}}}-1)$states is modified to cover$\mathrm{2^{\mathit{m}}}$states without degrading the counting rate. Based on the property that only the low-order bits are frequently switched, the proposed counter consists of two sub-counters to achieve a high counting rate and reduce the hardware complexity needed to convert an LFSR state into a binary state. The low-order sub-counter is implemented with the proposed LFSR counter, and the high-order sub-counter is designed by employing the conventional synchronous binary counter. In addition, the implemented counter takes into account the speed degradation caused by the large fan-out of the high-order sub-counter. The proposed counter designed with standard cells operates at 2.08 GHz in a 65 nm CMOS technology, and its counting rate is almost independent of the counter size. Hyungjoon Bae 0001, Yujin Hyun, Suchang Kim, Sangsoo Park, Jaeyoung Lee 0004, Boseon Jang, Suyoung Choi, In-Cheol Park |
IEEE Trans. Computers | 7 |