Dong S. Suk

dblp:21/1719 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 1981
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 84% Memory systems · 16%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
memory testing
0.021981
A March Test for Functional Faults in Semiconductor Random Access Memories · IEEE Trans. Computers 1981
Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories · IEEE Trans. Computers 1980
Electronic design automation › hardware verification and test › memory testing
march test algorithm
0.011981
A March Test for Functional Faults in Semiconductor Random Access Memories · IEEE Trans. Computers 1981
Memory systems
semiconductor memory
0.021981
A March Test for Functional Faults in Semiconductor Random Access Memories · IEEE Trans. Computers 1981
Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories · IEEE Trans. Computers 1980
YearPublicationVenuePosition
1981 A March Test for Functional Faults in Semiconductor Random Access Memories
abstract
A test procedure requiring 14 N operations to detect functional faults in semiconductor random access memories (RAM's) is given. It is shown that the proposed test procedure detects modeled types of functional faults if only one type of fault is present in the RAM under test. The test procedure given belongs to a class of tests called march tests. It is proved that any march test requires at least 14 N operations to detect the modeled faults. Next, groups of different types of functional faults that can be simultaneously present in the RAM under test and yet be detected by the proposed test procedure or a given enhanced test procedure (requiring 16 N operations) are studied.
Dong S. Suk, Sudhakar M. Reddy
IEEE Trans. Computers1
1980 Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories
abstract
A class of pattern-sensitive faults in semiconductor random-access memories are studied. Efficient test procedures to detect and locate modeled faults are presented.
Dong S. Suk, Sudhakar M. Reddy
IEEE Trans. Computers1