This paper presents an efficient algorithm for post-synthesis logic simulation of digital circuits with oscillatory combinational loops. Oscillatory combinational loops can significantly degrade the performance of cycle accurate logic simulators. We provide an algorithm that first, dynamically detects oscillatory loops. Then, we introduce a novel approach to compute a multiple of their oscillation period which is used to optimize the efficiency of the simulation by reducing the number of time points that need to be evaluated. Finally, we provide the experimental results of our optimized algorithm measured on a cycle accurate simulator used in conjunction with a hardware emulator.

Summary form only given. An input-queued switch with virtual output queuing is able to provide a maximum throughput of 100% in the supporting more sophisticated scheduling strategies. Switch scheduling can be cast as a maximum flow problem. We propose a maximum weight bipartite matching (MWBM) scheduling algorithm for input-queued switches. Our goal is to provide 100% throughput while maintaining fairness and stability. Our algorithm provides sublinear parallel run time complexity using a polynomial number of processing elements. We are able to obtain the MWBM for a time slot in sublinear time by using the matching produced in the previous time slot based on the observation that in input-queued cell-based switches, the weight of edges changes very little during successive time slots. To the best of our knowledge, our algorithm outperforms all previously proposed MWBM scheduling algorithms proposed for input-queued switches. We also describe a linear time complexity MWBM algorithm for a general bipartite graph which outperforms the best known sublinear MWBM algorithm for any bipartite graph with less than 10/sup 15/ number of nodes.