Design features (e.g. reliability, maintainability, and testability) of systems designed to tolerate faults which could compromise the safe and secure operation of a system are discussed. Design automation issues are discussed with a focus on the future. The reliability of proposed systems is assessed using HARP, the hybrid automated reliability predictor, a software package for reliability prediction.>

The approaches currently used for adding testability into system designs are based on ad-hoc testing methods or on the experience of a design team supported by testing experts. This paper presents a design methodology and a knowledge-based CAD environment that allows a system designer to incorporate testability into a design in a formal, verifiable way which also provides clear documentation for this activity. Prototype CAD tools have been built and have met with limited in-house use success. The design and implementation of the current prototype tools, collectively known as the Test Engineer's Assistant (TEA) tools, along with lessons learned and elements of a more robust system will be presented.>

A methodology and the supporting CAD (computer-aided design) tools are discussed for designing a digital system so that it can meet predefined testability requirements. The set of tools is called the Test Engineer's Assistant (TEA). The TEA system creates an environment in which the designer can perform performance assessment, functional design, and design for testability (DFT). TEA is developed to support automated DFT at the board and subsystem levels, to aid in an appropriate choice of BIT (built-in test) techniques at the board level that is supported at the subsystem and system levels, to indicate where to augment system function with predefined BIT modules to increase testability, and to assess the hardware costs of implementing DFT and BIT.>

The performance and cost of a modulo-3 residue code checker that has been attached to a pipelined serial multiplier to provide a concurrent self-test capability are considered. Analytical results are derived for error detection coverage and minimum error latency; these quantities are observed to be in agreement with simulation results obtained by using ISPS, a register-transfer language. The residue checker error detection coverage and minimum error latency are observed to be dependent on the statistical properties of the multiplier input operands. The checker and serial multiplier were implemented in 4- mu m NMOS, using a standard cell design. The residue code checker required approximately half of the total silicon area.>