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Etsuko Okushi

dblp:21/3592 · DBLP profile ↗
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3ranked-venue papers
0as first author
0since 2021 · last 2000
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2Artificial intelligence and machine learning · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Reconfigurable computing and FPGAs · 60% Embedded and real-time systems · 31% Processor architecture and microarchitecture · 9%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs › FPGA accelerator
FPGA-based genetic algorithm		 0.012000
An FPGA-based genetic algorithm machine (poster abstract) · FPGA 2000
Compilers and program optimization › compiler construction
compiler generation		 0.011997
Memory-CPU Size Optimization for Embedded System Designs · DAC 1997
Embedded and real-time systems
embedded system design		 0.011997
Memory-CPU Size Optimization for Embedded System Designs · DAC 1997
Reconfigurable computing and FPGAs › FPGA accelerator
FPGA coprocessor		 0.012000
An FPGA-based genetic algorithm machine (poster abstract) · FPGA 2000

Methods — techniques the papers use, named apart from their topics

system cost minimization · 0.0genetic algorithm · 0.0
YearPublicationVenuePosition
2000 An FPGA-based genetic algorithm machine (poster abstract)
abstract
No abstract available.
Barry Shackleford, Etsuko Okushi, Mitsuhiro Yasuda, Hisao Koizumi, Katsuhiko Seo, Takashi Iwamoto, Hiroto Yasuura
 FPGA2
1997 Memory-CPU Size Optimization for Embedded System Designs
abstract
Entire systems embedded in a chip and consistingof a processor, memory, and system-specific peripheral hardwareare now commonly contained in commodity electronicdevices. Cost minimization of these systems is of paramounteconomic importance to manufactures of these devices. Byemploying a variable configuration processor in conjunctionwith a multi-precision compiler generator there are situationsin which considerable system cost reduction can be obtainedby synthesizing a CPU that is narrower than the largest variablein the application program.
Barry Shackleford, Mitsuhiro Yasuda, Etsuko Okushi, Hisao Koizumi, Hiroyuki Tomiyama, Hiroto Yasuura
 DAC3
1997 A High-Performance Hardware Implementation of a Survival-Based Genetic Algorithm
Barry Shackleford, Etsuko Okushi, Mitsuhiro Yasuda, Hisao Koizumi, Katsuhiko Seo, Takashi Iwamoto, Hiroto Yasuura
 ICONIP (1)2