Hardware spiking neural networks that co-integrate analog silicon neurons with memristive synaptic crossbar arrays are promising candidates to achieve low-power processing of event-based data. Learning patterns with real-world timescales, often exceeding the millisecond range, is however difficult with fully analog systems. In this work, we propose to overcome this challenge by introducing mixed-signal strategies to implement hardware-friendly learning rules derived from Spike Timing-Dependent Plasticity. By system-level simulation means, we illustrate the potential of this concept for both unsupervised and reward-modulated learning. In particular, we investigate how such learning rules and their tuning impact the overall system recognition rate depending on different characteristics of event-based inputs or synapses. This work provides useful insights for building versatile energy-efficient event-based neuromorphic systems with online learning capability.

Since memristor came out in 2008, neuromorphic designers investigated the possibility of using memristors as plastic synapses due to their intrinsic properties of plasticity and weight storage. In this paper we will present a silicon neuron compatible with memristive synapses in order to build analog neural network. This neuron mainly includes current conveyor (CCII) for driving memristor as excitatory or inhibitory synapses and spike generator whose waveform is dedicated to synaptic plasticity algorithm based on Spike Timing Dependent Plasticity (STDP). This silicon neuron has been fabricated, characterized and finally connected with a ferroelectric memristor to validate the synaptic weight updating principle.

Neuromorphic chips are composed of silicon neurons, synapses and memories for synaptic weight. Moreover we can find a fourth part dedicated to synaptic plasticity algorithm. Even though we can find some low-power silicon neurons, the power consumption reduction of synapses, memories and plasticity algorithm is not enough explored. Since memristor coming-out in 2008, neuromorphic designers investigate the possibility of using memristors as plastic synapses due to their intrinsic property of plasticity. This nanocomponent gathers the function of synapse, the weight storage and the plasticity. So far, the proposed solutions cannot manage both excitatory and inhibitory memristive synapses with one single design. In this paper we will present an elegant solution based on current conveyor (CCII) for driving memristor as excitatory or inhibitory synapses following the neural network implementation.

Reuse methodologies are now widely used to design digital circuits. They are based on the concept of intellectual property (IP), or virtual block of computing, characterized by a behavioral model, synthesizable or not. The design reuse for analog integrated systems is much less natural and less standardized. This paper addresses the issue of an analog design flow based on reuse, focusing on three key issues: the formal content of the IP block, the design of a reusable analog IP, and the organization of a design flow centered on an IP library. After a conceptual overview, this paper presents the methodological principles and details examples with a tutorial intention. The objective is to guide the designer involved in the process of developing analog IPs and corresponding design flow. This method is inspired by platform-based design and adapted here on an original case study: the design of full-custom neuromimetic integrated circuits, built from specific analog computational blocks. The development of reusable IPs represents an additional effort, mainly for behavioral modeling and characterization. Nevertheless, the steps illustrated in this case study show that the extra time provides a definite advantage to future design projects.

In this paper, we present an hardware implementation of spiking neural networks based on analog integrated circuits. These ICs compute in real-time a biologically realistic neuron models. Each integrated circuit includes five neurons and analog memory cells to set and store the conductance model parameters, and eventually optimize it to compensate the analog circuit variability. The circuits are embedded in a multi-board system all connected to a backplane with daisy-chain facilities. Each action potential computed by analog neuromimetic chips is time-stamped when detected by digital device (FPGA). These FPGAs are also in charge of the real-time plasticity computation and of controlling inter-boards communication. The implemented neural plasticity is also biological relevant thanks to its time dependent computation. The whole system is designed to compute programmable models and connectivity schemes.

Large-scale spiking neural networks (SNN) are generally run on distributed and parallel architectures with multiple computation nodes. These architectures induce extra delays due to the node-to-node communication process. In multiboard & multichip SNNs, important delays may affect spike arrival time and, thus, can alter simulation results. In this work, we propose a method aiming to guarantee spike arrival time with arbitrary prefixed deadlines. The communication architecture is based on the token-passing access policy to grant access to shared communication channels. We show that several network parameters must be set carefully if spikes have to meet their deadlines. Parameters are chosen by taking into account the communication channel bandwidth, the arbitrary deadlines and the worst case situation that can happen in generating neural activity in SNNs. As proof of concept, we have built a system that emulates up to 120 analog Hodgkin-Huxley neurons spread across 6 boards. Experimental results show that whatever it happens (unless there is a network fault), spikes reach their destination with a maximum delay of 5 microseconds.

In this paper, we present a multi-board system based on analog neuromimetic ICs. These ICs compute in realtime conductance-based models. These models are implemented in a modular architecture based on our analog IPs. Each IC includes five neurons and analog memory cells to set and store the conductance model parameters, and eventually optimize it to compensate the analog circuit variability. The circuits are embedded in a multi-board system able to host up to 120 neurons spread across 6 boards all connected to a backplane with daisy-chain facilities. Each action potential computed by analog neuromimetic chips is time-stamped when detected by digital device (FPGA). These FPGAs are also in charge of the real-time plasticity computation and of controlling inter-boards communication. The system is designed to compute programmable models and connectivity schemes.

This paper presents an original method to tune a neuromimetic IC based on neuron conductance-based models (Hodgkin-Huxley formalism). This method is well known in electrophysiology as the "voltage-clamp" technique. It consists in measuring the neural conductances while holding the membrane voltage at a clamped level. The voltage- and time- dependent variables of the conductance equations are then interpolated from the measurements. We apply this technique on the neuromimetic IC to extract the exact parameters of the neuron model. This model is computed in software, and results are compared with the hardware simulation. We conclude by mentioning the potential applications of this technique in hardware simulation systems based on neuromimetic ASICs.

This paper aims at discussing the implementation of simulation systems for SNN based on analog computation cores (neuromimetic ICs). Such systems are an alternative to completely digital solutions for the simulation of spiking neurons or neural networks. Design principles for the neuromimetic ICs and the hosting systems are presented together with their features and performances. The authors summarize the existing architectures and neuron models used in such systems, when configured as stand-alone tools for simulating ANN or together with a neurophysiology set-up to study hybrid living artificial neural networks. As a primary illustration, the authors present results from one of the platforms: hardware simulations of single neurons and adaptive neural networks modeled using the Hodgkin-Huxley formalism for point neurons and spike-timing dependent plasticity algorithms for the network adaptation. Additional examples are detailed in the other papers of the session.

This paper presents an analog neuromimetic integrated circuit and an associated system dedicated for experiments of parameters extraction in biological neuron models. The IC based on Hodgkin-Huxley (HH) formalism computes in real-time and continuous mode. The dedicated system is a PCI board that is able to program dynamically the neuron model parameters in the IC. The full system, which includes the IC and the PCI board, is used to build a new hardware/software technique to extract biophysics parameters from biological neuron. This technique could be helpful for the neuroscientists proposing an alternative to voltage-clamp technique. For that, the new technique will use optimization algorithms to be efficient