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Jens Franke

dblp:21/4908 · DBLP profile ↗
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5ranked-venue papers
1as first author
0since 2021 · last 2010
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Security and privacy · 3 · 1 first-authorSystems, architecture and hardware · 1Human-computer interaction and ubiquitous computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
3 papers
Cryptographic primitives and cryptanalysis · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 5 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Cryptographic primitives and cryptanalysis
integer factorization
0.232010
Factorization of a 768-Bit RSA Modulus · CRYPTO 2010
A Kilobit Special Number Field Sieve Factorization · ASIACRYPT 2007
SHARK: A Realizable Special Hardware Sieving Device for Factoring 1024-Bit Integers · CHES 2005
Cryptographic primitives and cryptanalysis › public-key cryptography
RSA
0.122010
Factorization of a 768-Bit RSA Modulus · CRYPTO 2010
A Kilobit Special Number Field Sieve Factorization · ASIACRYPT 2007
Cryptographic primitives and cryptanalysis › public-key cryptography
public-key cryptanalysis
0.112010
Factorization of a 768-Bit RSA Modulus · CRYPTO 2010
Integrated circuit design › digital circuit design
cryptographic hardware
0.112005
SHARK: A Realizable Special Hardware Sieving Device for Factoring 1024-Bit Integers · CHES 2005
Cryptographic primitives and cryptanalysis
public-key cryptography
0.012007
A Kilobit Special Number Field Sieve Factorization · ASIACRYPT 2007

Methods — techniques the papers use, named apart from their topics

number field sieve · 0.1special number field sieve · 0.1
YearPublicationVenuePosition
2010 Factorization of a 768-Bit RSA Modulus
Thorsten Kleinjung, Kazumaro Aoki, Jens Franke, Arjen K. Lenstra, Emmanuel Thomé, Joppe W. Bos, Pierrick Gaudry, Alexander Kruppa, Peter L. Montgomery, Dag Arne Osvik, Herman J. J. te Riele, Andrey Timofeev, Paul Zimmermann 0001
CRYPTO3
2009 Chemieraum: tangible chemistry in exhibition space
abstract
This paper describes a new interactive exhibit that should motivate young people to easily explore the field of chemistry with the help of a tabletop interface. This interface is controlled by a new input device equipped with a haptic and visual feedback.
Thomas Gläser, Jens Franke, Götz Wintergerst, Ron Jagodzinski
TEI2
2007 A Kilobit Special Number Field Sieve Factorization
Kazumaro Aoki, Jens Franke, Thorsten Kleinjung, Arjen K. Lenstra, Dag Arne Osvik
ASIACRYPT2
2005 SHARK: A Realizable Special Hardware Sieving Device for Factoring 1024-Bit Integers
Jens Franke, Thorsten Kleinjung, Christof Paar, Jan Pelzl, Christine Priplata, Colin Stahlke
CHES1
2005 Hardware Factorization Based on Elliptic Curve Method
abstract
The security of the most popular asymmetric cryptographic scheme RSA depends on the hardness of factoring large numbers. The best known method for factorization large integers is the general number field sieve (GNFS). Recently, architectures for special purpose hardware for the GNFS have been proposed. One important step within the GNFS is the factorization of mid-size numbers for smoothness testing, an efficient algorithm for which is the elliptic curve method (ECM). Since the smoothness testing is also suitable for parallelization, it is promising to improve ECM via special-purpose hardware. We show that massive parallel and cost efficient ECM hardware engines can improve the cost-time product of the RSA moduli factorization via the GNFS considerably. The computation of ECM is a classical example for an algorithm that can be significantly accelerated through special-purpose hardware. In this work, we present an efficient hardware implementation of ECM to factor numbers up to 200 bits, which is also scalable to other bit lengths. For proof-of-concept purposes, ECM is realized as a software-hardware co-design on an FPGA and an embedded microcontroller. This appears to be the first publication of a realized hardware implementation of ECM, and the first description of GNFS acceleration through hardware-based ECM.
Martin Simka, Jan Pelzl, Thorsten Kleinjung, Jens Franke, Christine Priplata, Colin Stahlke, Milos Drutarovský, Viktor Fischer
FCCM4