Image rectification is one of the most complex pre-processing techniques for multi-view video coding (MVC). It corrects image distortion and simplifies MVC matching operations by transforming images into a standard coordinate system. Therefore, the rectification can improve both image quality and coding efficiency for MVC. In this paper, we propose two low complexity image rectification schemes for MVC: view-selective preprocessing rectification and view-selective pre- and post-processing rectification. The proposed algorithm does not perform frames of all views but few selected views which do not affect MVC performances. The experimental results show that the proposed rectification schemes feature much lower complexity without degrading image quality than the existing approach.

This paper demonstrates the benefits of hardwiring two of the main RTOS functionalities for multitasking environment. They are context switching and software interrupt processing operations. In particular, the paper proposes reconfiguring the FPGA which includes the proposed one time reconfigurable CPU and RTOS hardware, optimized for a given application by tailoring the entire hardware around the particular tasks involved. As a demonstration, the proposed RTOS hardware was designed and tested on a multichannel speaker system application to yield 60% performance increase over the conventional software- based RTOS.

Techniques are proposed for computing a global virtual time (GVT), which is the minimum local virtual time of processes in Time Warp. The algorithm computes a conservative estimate of GVT using an approach which is considerably simpler than previous algorithms for computing GVT. This algorithm does not require a global synchronization of processors. An inherent problem is GVT computation relates to handling messages in transit. Several alternatives are proposed for solving the transient message problem. The algorithm is suitable for distributed shared memory machines such as the BBN Butterfly and message passing machines with a variety of interconnection networks.>

Three efficient parallel logic simulation techniques for the Connection Machine are developed. The first technique which uses a global clock, is a synchronous version of a traditional simulation technique. The second technique is a hybrid of both the synchronous simulation technique with a global clock and the Chandy-Misra algorithm for asynchronous event processing. The third technique, called a simulation time lookahead technique, is proposed to make the second technique more optimistic than the Chandy-Misra algorithm by predicting in advance the timestamp of the next event. Experimental results show that the three techniques achieve better performance than the Time Warp protocol on the Connection Machine. The proposed techniques are several hundred times faster than the VHDL simulator on a SUN3, especially for circuits with very large number of gates.>

A dynamic hashing scheme that guarantees single access retrieval from the disk is proposed. This is based on the external hashing scheme proposed by G.H. Gonnet and P.A. Larson (see JACM, vol.35, no.1, p.161-84, 1988). The performance of the scheme is achieved at the cost of a small amount of internal memory which remains proportional to the file size. The necessary algorithms for address computation, insertions and file expansions are presented. Since theoretical analysis appears too difficult, the performance is studied using simulations with real-life files.>