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Kaiyuan Huang

dblp:21/5970 · DBLP profile ↗
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9ranked-venue papers
4as first author
3since 2021 · last 2024
0009-0009-3133-5472ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 7 · 4 first-author · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
4 papers
Electronic design automation · 93% Distributed systems · 5% Hardware reliability and fault tolerance · 2%

Topics — the 10 heaviest of 10, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
fault diagnosis
0.031998
Diagnosis of clustered faults and wafer testing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1998
A Diagnosis Algorithm for Constant Degree Structures and Its Application to VLSI Circuit Testing · IEEE Trans. Parallel Distributed Syst. 1995
Almost Sure Diagnosis of Almost Every Good Element · IEEE Trans. Computers 1994
Electronic design automation
hardware verification and test
0.021998
Diagnosis of clustered faults and wafer testing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1998
A Diagnosis Algorithm for Constant Degree Structures and Its Application to VLSI Circuit Testing · IEEE Trans. Parallel Distributed Syst. 1995
Electronic design automation › hardware verification and test › VLSI testing
wafer testing
0.021998
Diagnosis of clustered faults and wafer testing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1998
Almost Sure Diagnosis of Almost Every Good Element · IEEE Trans. Computers 1994
Electronic design automation › hardware verification and test › fault diagnosis
system-level diagnosis
0.021995
A Diagnosis Algorithm for Constant Degree Structures and Its Application to VLSI Circuit Testing · IEEE Trans. Parallel Distributed Syst. 1995
On the Diagnosis of System Faults with Propagation · IEEE Trans. Computers 1986
Electronic design automation › hardware verification and test
VLSI testing
0.011995
A Diagnosis Algorithm for Constant Degree Structures and Its Application to VLSI Circuit Testing · IEEE Trans. Parallel Distributed Syst. 1995
Distributed systems
fault tolerance
0.021995
A Diagnosis Algorithm for Constant Degree Structures and Its Application to VLSI Circuit Testing · IEEE Trans. Parallel Distributed Syst. 1995
On the Diagnosis of System Faults with Propagation · IEEE Trans. Computers 1986
Electronic design automation
yield analysis
0.011998
Diagnosis of clustered faults and wafer testing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1998
Hardware reliability and fault tolerance › network fault tolerance
fault diameter
0.011995
A Diagnosis Algorithm for Constant Degree Structures and Its Application to VLSI Circuit Testing · IEEE Trans. Parallel Distributed Syst. 1995
Electronic design automation
fault propagation
0.011986
On the Diagnosis of System Faults with Propagation · IEEE Trans. Computers 1986
Electronic design automation › hardware verification and test › fault diagnosis › system-level diagnosis
sequential diagnosis
0.011986
On the Diagnosis of System Faults with Propagation · IEEE Trans. Computers 1986

Methods — techniques the papers use, named apart from their topics

probabilistic diagnosis · 0.0negative binomial failure distribution · 0.0binomial failure distribution · 0.0digraph model · 0.0comparison model · 0.0fault model · 0.0diagnosability criteria · 0.0
YearPublicationVenuePosition
2024 Cyber Security Risk Assessment of Intelligent Ships under Multi-source Attacks
abstract
Automated and semi-automated ships have developed rapidly in recent years, but various external communication links have introduced some external threats. To solve the unknown impact of multiple attacks on intelligent ships, a cellular automaton is proposed to model the risk propagation process. We identify risk assessment indicators from the perspective of attack-defense confrontation and analyze the risk propagation situation from six different angles. Based on the experimental results, we identify the system’s weak nodes and propose cyber security protection suggestions to reduce the loss caused by multisource attacks on the system.
Kaiyuan Huang, Xiaoya Hu
HPCC2
2023 Design of OvTDM Toward Enhanced Physical Layer Security
abstract
This paper focuses on addressing encryption and security concerns in wireless communications, by considering the utilizing of overlapped time domain multiplexing (OvTDM) to enhance transmission security. In this paper, a method is suggested in order to simultaneously balance the requirements of high speed rate and secure encryption in the communication process. Specifically, we propose a method for generating two-dimensional secret key by leveraging OvTDM's shaping filter parameters. The proposed approach enables secure and encrypted transmissions at the physical layer, contributing to improved communication security.
Chongda Huang, Kaiyuan Huang
ISNCC2
2023 Application of knowledge graph in software engineering field: A systematic literature review
Lu Wang 0014, Chenhan Sun, Weikun Nie, Kaiyuan Huang
Inf. Softw. Technol.5
1998 Diagnosis of clustered faults and wafer testing
abstract
A probabilistic diagnosis algorithm is presented for constant degree structures. The performance of the algorithm is analyzed under a negative binomial failure distribution to account for fault clustering. It is shown that the algorithm can correctly identify almost all units even when the yield is low (much lower than 50%) and when faults are clustered. A wafer test structure is proposed, which utilizes the test access port of each die to perform comparison tests on its neighbors and incorporates a localized version of the diagnosis algorithm to determine the status of each die. Both the test time and the diagnosis time are invariant with respect to the number of dies on the wafer. The saving of test costs could be significant as compared with probe testing, because with probe testing dies are probed one at a time while they are tested in parallel with this scheme. The scheme is unique in that it is shown to work well when faults are clustered and when the yield is low.
Kaiyuan Huang, Vinod K. Agarwal, Krishnaiyan Thulasiraman
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
1995 A Diagnosis Algorithm for Constant Degree Structures and Its Application to VLSI Circuit Testing
abstract
A simple diagnosis algorithm is presented for constant degree systems such as rectangular grids connected as tori. The algorithm determines the status of a unit according to the size of its faction, a cluster of units that call each other fault-free but outsiders faulty. Almost all units are correctly identified with this algorithm under a binomial failure distribution even when the probability of failure is rather high. The complexity of the algorithm is O(n), where n is the number of units in a constant degree system. The application of the algorithm to production testing of VLSI chips is also considered. With a test board that houses a large number of chips to be tested, all the chips can be tested in parallel in a way that they test each other and the test outcomes, not necessarily correct, are reported to a host system for analysis. The actual status of each chip is determined by using this new diagnosis algorithm. The above chip screening process can be repeated for higher accuracy. It is shown that no more than two steps are needed in most real situations. Compared with testing by test equipment that usually tests only one chip at a time, the saving of test time and the test equipment cost could be significant with our approach.>
Kaiyuan Huang, Vinod K. Agarwal, Laurence E. LaForge, Krishnaiyan Thulasiraman
IEEE Trans. Parallel Distributed Syst.1
1994 Almost Sure Diagnosis of Almost Every Good Element
abstract
We demonstrate a structure for mutual test among N processing elements. We indicate how this structure might be used to identify the good dice on a semiconductor wafer at a cost below that of current techniques. Under either a digraph or a comparison model, our proposed test structure has the following properties: 1) It is nearly regular. 2) It can be laid out in area O(/spl ominus/(n). 3) In time /spl ominus/(N) and with high probability, all but at most an arbitrarily small fraction of the good elements can be identified. 4) The number of tests or comparisons per element is bounded by a constant. We approximate this constant analytically. The result is a substantial savings over the /spl ominus/(log N) tests per element in regular structures whose purpose is to identify, with high probability, every good element. In contrast with the majority of previous work, our results apply even when less than half of the elements are good.>
Laurence E. LaForge, Kaiyuan Huang, Vinod K. Agarwal
IEEE Trans. Computers2
1988 Diagnosability of system faults with propagation under asymmetric invalidation
Kaiyuan Huang
Microprocess. Microprogramming1
1987 Parallel testing for system diagnosis and a scheduling algorithm
Ping Ni, Kaiyuan Huang
Microprocessing and Microprogramming2
1986 On the Diagnosis of System Faults with Propagation
abstract
This correspondence proposes a new fault model for system diagnosis, wherein the interaction among faulty subsystems and fault propagation is considered. Criteria for one-step diagnosability are given. Optimal design of diagnosable systems is also developed. As to sequential diagnosis, single-loop systems are studied in depth.
Kaiyuan Huang, Tinghuai Chen
IEEE Trans. Computers1