I/sub DDQ/ testing, along with stuck-at fault, AC timing, and DC testing is increasingly considered a necessity for good product quality. This paper presents an I/sub DDQ/ vector selection methodology, along with vector implementation in the production test program. I/sub DDQ/ fault seeding results show that by stuck-at fault modeling, we can detect single stuck-at nodes that were not detected before. A comparative evaluation of conventional testing methods and I/sub DDQ/ testing is presented. Experimental test results are presented that ascertain the effectiveness of I/sub DDQ/ particularly how it overlaps with stuck-at fault coverage. A practical method that estimates the test coverage overlap is applied to reduce the stuck-at improvement effort and obtain "credit" towards the Intel386 EX processor quality requirements for production. A follow-on experiment for obtaining more data is proposed and data are being collected.

Identification and removal of redundancy in digital circuits is important for improving their testability as well as reducing their area. This paper presents a method of identifying and removing redundancy in combinational circuits by analyzing circuit structure. Experimental results indicate that the method is quite efficient in execution time, but may not identify all undetectable faults. It is expected to be suitable for integration into a logic synthesis system. It can also be used as a preprocessor for a test pattern generation program or for a test pattern generation based redundancy removal program.>

Redundancy in combinational circuits is usually identified when faults are found to be undetectable during test generation. Redundancy removal based on test generation is not efficient, because removal of the redundancy causing a fault to be undetectable will usually affect the detectability of other faults, making it necessary to repeat test generation. The authors present a method of identifying and removing redundancy in combinational circuits by analyzing regions between fanout stems and reconvergence gates, and experimental results for the ISCAS85 benchmark circuits.>